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- Jul 17, 2018
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Leo Liu authored
Fixes: 2c773de2 (drm/amdgpu: defer test IBs on the rings at boot (V3)) Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- Jun 19, 2018
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Harry Wentland authored
We've had a number of users report failures to detect and light up display with DC with LVDS and VGA. These connector types are not currently supported with DC. I'd like to add support but unfortunately don't have a system with LVDS or VGA available. In order not to cause regressions we should probably fallback to the non-DC driver for ASICs that support VGA and LVDS. These ASICs are: * Bonaire * Kabini * Kaveri * Mullins ASIC support can always be force enabled with amdgpu.dc=1 v2: Keep Hawaii on DC v3: Added Mullins to the list Cc: stable@vger.kernel.org Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
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- Jun 13, 2018
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Huang Rui authored
After defer the execution of clockgating enabling, at that time, gfx already enter into "off" state. Howerver, clockgating enabling will use MMIO to access the gfx registers, then get the gfx hung. So here we should move the gfx powergating and gfxoff enabling behavior at the end of initialization behind clockgating. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
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- May 24, 2018
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Rex Zhu authored
VCN clockgating is handled manually like VCE and UVD. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
First of all it's already being called from the display code from amd_ip_funcs.suspend/resume hooks. Second of all, the place in amdgpu_device_gpu_recover it's being called is wrong for GPU stalls since it is called BEFORE we cancel and force completion of all in flight jobs which were not yet processed. So, as Bas pointed in the ticket we will try to wait for fence in amdgpu_pm_compute_clocks but the pipe is hanged so we end up in deadlock. v2: remove unused variable Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106500 Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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- May 17, 2018
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Feifei Xu authored
v2: fix whitespace Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
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Feifei Xu authored
Reviewed-by:
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Feifei Xu authored
vega20_gpu_info firmware stores gpu configuration for vega20. v2: drop gpu info firmware for vega20 Squash of: drm/amdgpu: Add gpu_info firmware for vega20. drm/amdgpu: drop gpu_info firmware for vega20 Reviewed-by:
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Feifei Xu authored
Add vega20 to amd_asic_type enum and amdgpu_asic_name[]. Reviewed-by:
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- May 15, 2018
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Emily Deng authored
When put the IB test out of exclusive mode, and do sriov reset, the IB test will randomly fail. As out of exclusive mode it uses kiq to do read and write registers, but as it has world switch, the kiq read and write time will be random, sometimes it will beyond the MAX_KIQ_REG_WAIT and then the read or write register will fail, which will result the IB test fail. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Leo Liu authored
Signed-off-by:
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Leo Liu authored
Signed-off-by:
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Leo Liu authored
Signed-off-by:
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Leo Liu authored
Signed-off-by:
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Huang Rui authored
Signed-off-by:
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Huang Rui authored
Signed-off-by:
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Rex Zhu authored
v2: check reserved vram size before allocate. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Shirish S authored
amdgpu_ib_ring_tests() runs test IB's on rings at boot contributes to ~500 ms of amdgpu driver's boot time. This patch defers it and ensures that its executed in amdgpu_info_ioctl() if it wasn't scheduled. V2: Use queue_delayed_work() & flush_delayed_work(). V3: removed usage of separate wq, ensure ib tests is run before enabling clockgating. Signed-off-by:Shirish S <shirish.s@amd.com> Reviewed-by:
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Harry Wentland authored
We enabled this upstream by default now and no longer need the flag. Signed-off-by:
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- Apr 11, 2018
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Alex Deucher authored
Use the new callback to determine whether to use full asic reset or per IP soft reset. Enables reset to actually proceed on asics which don't support soft reset yet. Reviewed-by:
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Daniel Stone authored
Since drm_framebuffer can now store GEM objects directly, place them there rather than in our own subclass. As this makes the framebuffer create_handle and destroy functions the same as the GEM framebuffer helper, we can reuse those. Acked-by:
Daniel Stone <daniels@collabora.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: David (ChunMing) Zhou <David1.Zhou@amd.com> Cc: amd-gfx@lists.freedesktop.org Signed-off-by:
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Rex Zhu authored
Reviewed-by:
Christian <König<christian.koenig@amd.com> Signed-off-by:
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- Mar 21, 2018
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Andrey Grodzovsky authored
Problem: When unloading due to failure amdgpu_device_fini was called twice which was leading to NULL ptr in amdgpu_irq_disable_all. Fix: Call amdgpu_device_fini only once from amdgpu_driver_unload_kms. Reviewed-by:
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Alex Deucher authored
DC is used for modesetting on vega12. Acked-by:
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Alex Deucher authored
soc15 just like vega10 and raven. Acked-by:
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Alex Deucher authored
Stores gpu configuration details. Acked-by:
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Feifei Xu authored
Add vega12 to amd_asic_type enum and amdgpu_asic_name[]. Acked-by:
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Rex Zhu authored
Reviewed-by:
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Mikita Lipski authored
By moving amdgpu_irq_disable_all earlier in the sequence fixes an issue with disabling pflip interrupts: *ERROR* dal_irq_service_dummy_ack: called for non-implemented irq source Earlier patch fixed a memory corruption and revealed irq warnings.This way it seems to be there no obvious issues with unloading the module. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Mikita Lipski authored
Disable irq on devices before destroying them. That prevents use-after-free memory access when unloading the driver. Signed-off-by:
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Mikita Lipski authored
This change fixes the deadlock when unloading the driver with displays connected. Signed-off-by:
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Alex Deucher authored
Add kernel doc for the functions in amdgpu_device.c Signed-off-by:
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- Mar 15, 2018
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Mikita Lipski authored
This change fixes the deadlock when unloading the driver with displays connected. Signed-off-by:
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Rex Zhu authored
make it symmetric with amdgpu_ucode_init_bo in amd_powerplay.c refine the "commit b22558bb4ff8fc9fe925222f90297d7a03a5fb20" Reviewed-by:
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Rex Zhu authored
Reviewed-by:
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Rex Zhu authored
Reviewed-by:
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- Mar 14, 2018
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Alex Deucher authored
No need to replicate it in several places. Reviewed-by:
Rex Zhu <rezhu@amd.com> Acked-by:
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Alex Deucher authored
No need to replicate it in several places. Reviewed-by:
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Monk Liu authored
mailbox registers can be accessed with a byte boundry according to BIF team, so this patch prepares register byte access and will be used by following patches. Actually, for mailbox registers once the byte field is touched even not changed, the mailbox behaves, so we need the byte width accessing to those sort of regs. Signed-off-by:
Pixel Ding <Pixel.Ding@amd.com> Signed-off-by:
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Emily Deng authored
The amdgpu_ucode_fini_bo should be called after gfx_v8_0_hw_fini, or it will have KCQ disable failed issue. For Tonga, as it firstly finishes SMC block, and the SMC hw fini will call amdgpu_ucode_fini, which will lead the amdgpu_ucode_fini_bo called before gfx_v8_0_hw_fini, this is incorrect. Signed-off-by:
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