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Commit ea1f1437 authored by Anson Huang's avatar Anson Huang Committed by Leonard Crestez
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MLK-21393 soc: imx: update SCFW API 


This patch updates SCFW API to v1.7, based on below commit:

252281d48647 ("SCF-105: Update wiki.")

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: default avatarBai Ping <ping.bai@nxp.com>
(cherry picked from commit d6262556)
parent dbc9abcf
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with 312 additions and 139 deletions
drivers/soc/imx/sc/main/rpc.h
+ 1
− 1
View file @ ea1f1437
......@@ -20,7 +20,7 @@
/* Defines */
#define SCFW_API_VERSION_MAJOR 1U
#define SCFW_API_VERSION_MINOR 4U
#define SCFW_API_VERSION_MINOR 7U
#define SC_RPC_VERSION 1U
......
drivers/soc/imx/sc/svc/misc/rpc.h
+ 37
− 36
View file @ ea1f1437
......@@ -23,42 +23,43 @@
* @name Defines for RPC MISC function calls
*/
/*@{*/
#define MISC_FUNC_UNKNOWN 0 /* Unknown function */
#define MISC_FUNC_SET_CONTROL 1U /* Index for misc_set_control() RPC call */
#define MISC_FUNC_GET_CONTROL 2U /* Index for misc_get_control() RPC call */
#define MISC_FUNC_SET_MAX_DMA_GROUP 4U /* Index for misc_set_max_dma_group() RPC call */
#define MISC_FUNC_SET_DMA_GROUP 5U /* Index for misc_set_dma_group() RPC call */
#define MISC_FUNC_SECO_IMAGE_LOAD 8U /* Index for misc_seco_image_load() RPC call */
#define MISC_FUNC_SECO_AUTHENTICATE 9U /* Index for misc_seco_authenticate() RPC call */
#define MISC_FUNC_SECO_FUSE_WRITE 20U /* Index for misc_seco_fuse_write() RPC call */
#define MISC_FUNC_SECO_ENABLE_DEBUG 21U /* Index for misc_seco_enable_debug() RPC call */
#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U /* Index for misc_seco_forward_lifecycle() RPC call */
#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U /* Index for misc_seco_return_lifecycle() RPC call */
#define MISC_FUNC_SECO_BUILD_INFO 24U /* Index for misc_seco_build_info() RPC call */
#define MISC_FUNC_SECO_CHIP_INFO 25U /* Index for misc_seco_chip_info() RPC call */
#define MISC_FUNC_SECO_ATTEST_MODE 27U /* Index for misc_seco_attest_mode() RPC call */
#define MISC_FUNC_SECO_ATTEST 28U /* Index for misc_seco_attest() RPC call */
#define MISC_FUNC_SECO_GET_ATTEST_PKEY 31U /* Index for misc_seco_get_attest_pkey() RPC call */
#define MISC_FUNC_SECO_GET_ATTEST_SIGN 29U /* Index for misc_seco_get_attest_sign() RPC call */
#define MISC_FUNC_SECO_ATTEST_VERIFY 30U /* Index for misc_seco_attest_verify() RPC call */
#define MISC_FUNC_SECO_COMMIT 32U /* Index for misc_seco_commit() RPC call */
#define MISC_FUNC_DEBUG_OUT 10U /* Index for misc_debug_out() RPC call */
#define MISC_FUNC_WAVEFORM_CAPTURE 6U /* Index for misc_waveform_capture() RPC call */
#define MISC_FUNC_BUILD_INFO 15U /* Index for misc_build_info() RPC call */
#define MISC_FUNC_API_VER 35U /* Index for misc_api_ver() RPC call */
#define MISC_FUNC_UNIQUE_ID 19U /* Index for misc_unique_id() RPC call */
#define MISC_FUNC_SET_ARI 3U /* Index for misc_set_ari() RPC call */
#define MISC_FUNC_BOOT_STATUS 7U /* Index for misc_boot_status() RPC call */
#define MISC_FUNC_BOOT_DONE 14U /* Index for misc_boot_done() RPC call */
#define MISC_FUNC_OTP_FUSE_READ 11U /* Index for misc_otp_fuse_read() RPC call */
#define MISC_FUNC_OTP_FUSE_WRITE 17U /* Index for misc_otp_fuse_write() RPC call */
#define MISC_FUNC_SET_TEMP 12U /* Index for misc_set_temp() RPC call */
#define MISC_FUNC_GET_TEMP 13U /* Index for misc_get_temp() RPC call */
#define MISC_FUNC_GET_BOOT_DEV 16U /* Index for misc_get_boot_dev() RPC call */
#define MISC_FUNC_GET_BOOT_TYPE 33U /* Index for misc_get_boot_type() RPC call */
#define MISC_FUNC_GET_BUTTON_STATUS 18U /* Index for misc_get_button_status() RPC call */
#define MISC_FUNC_ROMPATCH_CHECKSUM 26U /* Index for misc_rompatch_checksum() RPC call */
#define MISC_FUNC_BOARD_IOCTL 34U /* Index for misc_board_ioctl() RPC call */
#define MISC_FUNC_UNKNOWN 0 /* Unknown function */
#define MISC_FUNC_SET_CONTROL 1U /* Index for misc_set_control() RPC call */
#define MISC_FUNC_GET_CONTROL 2U /* Index for misc_get_control() RPC call */
#define MISC_FUNC_SET_MAX_DMA_GROUP 4U /* Index for misc_set_max_dma_group() RPC call */
#define MISC_FUNC_SET_DMA_GROUP 5U /* Index for misc_set_dma_group() RPC call */
#define MISC_FUNC_SECO_IMAGE_LOAD 8U /* Index for misc_seco_image_load() RPC call */
#define MISC_FUNC_SECO_AUTHENTICATE 9U /* Index for misc_seco_authenticate() RPC call */
#define MISC_FUNC_SECO_FUSE_WRITE 20U /* Index for misc_seco_fuse_write() RPC call */
#define MISC_FUNC_SECO_ENABLE_DEBUG 21U /* Index for misc_seco_enable_debug() RPC call */
#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U /* Index for misc_seco_forward_lifecycle() RPC call */
#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U /* Index for misc_seco_return_lifecycle() RPC call */
#define MISC_FUNC_SECO_BUILD_INFO 24U /* Index for misc_seco_build_info() RPC call */
#define MISC_FUNC_SECO_CHIP_INFO 25U /* Index for misc_seco_chip_info() RPC call */
#define MISC_FUNC_SECO_ATTEST_MODE 27U /* Index for misc_seco_attest_mode() RPC call */
#define MISC_FUNC_SECO_ATTEST 28U /* Index for misc_seco_attest() RPC call */
#define MISC_FUNC_SECO_GET_ATTEST_PKEY 31U /* Index for misc_seco_get_attest_pkey() RPC call */
#define MISC_FUNC_SECO_GET_ATTEST_SIGN 29U /* Index for misc_seco_get_attest_sign() RPC call */
#define MISC_FUNC_SECO_ATTEST_VERIFY 30U /* Index for misc_seco_attest_verify() RPC call */
#define MISC_FUNC_SECO_COMMIT 32U /* Index for misc_seco_commit() RPC call */
#define MISC_FUNC_DEBUG_OUT 10U /* Index for misc_debug_out() RPC call */
#define MISC_FUNC_WAVEFORM_CAPTURE 6U /* Index for misc_waveform_capture() RPC call */
#define MISC_FUNC_BUILD_INFO 15U /* Index for misc_build_info() RPC call */
#define MISC_FUNC_API_VER 35U /* Index for misc_api_ver() RPC call */
#define MISC_FUNC_UNIQUE_ID 19U /* Index for misc_unique_id() RPC call */
#define MISC_FUNC_SET_ARI 3U /* Index for misc_set_ari() RPC call */
#define MISC_FUNC_BOOT_STATUS 7U /* Index for misc_boot_status() RPC call */
#define MISC_FUNC_BOOT_DONE 14U /* Index for misc_boot_done() RPC call */
#define MISC_FUNC_OTP_FUSE_READ 11U /* Index for misc_otp_fuse_read() RPC call */
#define MISC_FUNC_OTP_FUSE_WRITE 17U /* Index for misc_otp_fuse_write() RPC call */
#define MISC_FUNC_SET_TEMP 12U /* Index for misc_set_temp() RPC call */
#define MISC_FUNC_GET_TEMP 13U /* Index for misc_get_temp() RPC call */
#define MISC_FUNC_GET_BOOT_DEV 16U /* Index for misc_get_boot_dev() RPC call */
#define MISC_FUNC_GET_BOOT_TYPE 33U /* Index for misc_get_boot_type() RPC call */
#define MISC_FUNC_GET_BOOT_CONTAINER 36U /* Index for misc_get_boot_container() RPC call */
#define MISC_FUNC_GET_BUTTON_STATUS 18U /* Index for misc_get_button_status() RPC call */
#define MISC_FUNC_ROMPATCH_CHECKSUM 26U /* Index for misc_rompatch_checksum() RPC call */
#define MISC_FUNC_BOARD_IOCTL 34U /* Index for misc_board_ioctl() RPC call */
/*@}*/
/* Types */
......
drivers/soc/imx/sc/svc/misc/rpc_clnt.c
+ 19
− 0
View file @ ea1f1437
......@@ -672,6 +672,25 @@ sc_err_t sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t * type)
return (sc_err_t)result;
}
sc_err_t sc_misc_get_boot_container(sc_ipc_t ipc, uint8_t *idx)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_GET_BOOT_CONTAINER);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (idx != NULL)
*idx = RPC_U8(&msg, 0U);
return (sc_err_t)result;
}
void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status)
{
sc_rpc_msg_t msg;
......
drivers/soc/imx/sc/svc/seco/rpc.h
+ 23
− 21
View file @ ea1f1437
......@@ -23,27 +23,29 @@
* @name Defines for RPC SECO function calls
*/
/*@{*/
#define SECO_FUNC_UNKNOWN 0 /* Unknown function */
#define SECO_FUNC_IMAGE_LOAD 1U /* Index for seco_image_load() RPC call */
#define SECO_FUNC_AUTHENTICATE 2U /* Index for seco_authenticate() RPC call */
#define SECO_FUNC_FORWARD_LIFECYCLE 3U /* Index for seco_forward_lifecycle() RPC call */
#define SECO_FUNC_RETURN_LIFECYCLE 4U /* Index for seco_return_lifecycle() RPC call */
#define SECO_FUNC_COMMIT 5U /* Index for seco_commit() RPC call */
#define SECO_FUNC_ATTEST_MODE 6U /* Index for seco_attest_mode() RPC call */
#define SECO_FUNC_ATTEST 7U /* Index for seco_attest() RPC call */
#define SECO_FUNC_GET_ATTEST_PKEY 8U /* Index for seco_get_attest_pkey() RPC call */
#define SECO_FUNC_GET_ATTEST_SIGN 9U /* Index for seco_get_attest_sign() RPC call */
#define SECO_FUNC_ATTEST_VERIFY 10U /* Index for seco_attest_verify() RPC call */
#define SECO_FUNC_GEN_KEY_BLOB 11U /* Index for seco_gen_key_blob() RPC call */
#define SECO_FUNC_LOAD_KEY 12U /* Index for seco_load_key() RPC call */
#define SECO_FUNC_GET_MP_KEY 13U /* Index for seco_get_mp_key() RPC call */
#define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */
#define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */
#define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */
#define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */
#define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */
#define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */
#define SECO_FUNC_FUSE_WRITE 20U /* Index for seco_fuse_write() RPC call */
#define SECO_FUNC_UNKNOWN 0 /* Unknown function */
#define SECO_FUNC_IMAGE_LOAD 1U /* Index for seco_image_load() RPC call */
#define SECO_FUNC_AUTHENTICATE 2U /* Index for seco_authenticate() RPC call */
#define SECO_FUNC_FORWARD_LIFECYCLE 3U /* Index for seco_forward_lifecycle() RPC call */
#define SECO_FUNC_RETURN_LIFECYCLE 4U /* Index for seco_return_lifecycle() RPC call */
#define SECO_FUNC_COMMIT 5U /* Index for seco_commit() RPC call */
#define SECO_FUNC_ATTEST_MODE 6U /* Index for seco_attest_mode() RPC call */
#define SECO_FUNC_ATTEST 7U /* Index for seco_attest() RPC call */
#define SECO_FUNC_GET_ATTEST_PKEY 8U /* Index for seco_get_attest_pkey() RPC call */
#define SECO_FUNC_GET_ATTEST_SIGN 9U /* Index for seco_get_attest_sign() RPC call */
#define SECO_FUNC_ATTEST_VERIFY 10U /* Index for seco_attest_verify() RPC call */
#define SECO_FUNC_GEN_KEY_BLOB 11U /* Index for seco_gen_key_blob() RPC call */
#define SECO_FUNC_LOAD_KEY 12U /* Index for seco_load_key() RPC call */
#define SECO_FUNC_GET_MP_KEY 13U /* Index for seco_get_mp_key() RPC call */
#define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */
#define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */
#define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */
#define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */
#define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */
#define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */
#define SECO_FUNC_FUSE_WRITE 20U /* Index for seco_fuse_write() RPC call */
#define SECO_FUNC_PATCH 21U /* Index for seco_patch() RPC call */
#define SECO_FUNC_START_RNG 22U /* Index for seco_start_rng() RPC call */
/*@}*/
/* Types */
......
drivers/soc/imx/sc/svc/seco/rpc_clnt.c
+ 36
− 0
View file @ ea1f1437
......@@ -433,4 +433,40 @@ sc_err_t sc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr)
return (sc_err_t)result;
}
sc_err_t sc_seco_patch(sc_ipc_t ipc, sc_faddr_t addr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
RPC_FUNC(&msg) = U8(SECO_FUNC_PATCH);
RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
RPC_U32(&msg, 4U) = U32(addr);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_seco_start_rng(sc_ipc_t ipc, sc_seco_rng_stat_t *status)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
RPC_FUNC(&msg) = U8(SECO_FUNC_START_RNG);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, SC_FALSE);
if (status != NULL)
*status = RPC_U32(&msg, 0U);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
/**@}*/
include/dt-bindings/soc/imx_rsrc.h
+ 1
− 1
View file @ ea1f1437
......@@ -37,7 +37,7 @@
#define SC_R_DC_0_BLIT2 21
#define SC_R_DC_0_BLIT_OUT 22
#define SC_R_PERF 23
#define SC_R_UNUSED5 24
#define SC_R_USB_1_PHY 24
#define SC_R_DC_0_WARP 25
#define SC_R_UNUSED7 26
#define SC_R_UNUSED8 27
......
include/soc/imx8/sc/svc/misc/api.h
+ 15
− 0
View file @ ea1f1437
......@@ -510,6 +510,21 @@ void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t * dev);
*/
sc_err_t sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t * type);
/*!
* This function returns the boot container index.
*
* @param[in] ipc IPC handle
* @param[out] idx pointer to return index
*
* Return \a idx = 1 for first container, 2 for second.
*
* @return Returns and error code (SC_ERR_NONE = success).
*
* Return errors code:
* - SC_ERR_UNAVAILABLE if index not passed by ROM
*/
sc_err_t sc_misc_get_boot_container(sc_ipc_t ipc, uint8_t *idx);
/*!
* This function returns the current status of the ON/OFF button.
*
......
include/soc/imx8/sc/svc/rm/api.h
+ 56
− 7
View file @ ea1f1437
......@@ -140,12 +140,21 @@ typedef uint8_t sc_rm_perm_t;
* - SC_ERR_UNAVAILABLE if partition table is full (no more allocation space)
*
* Marking as non-secure prevents subsequent functions from configuring masters in this
* partition to assert the secure signal. If restricted then the new partition is limited
* in what functions it can call, especially those associated with managing partitions.
* partition to assert the secure signal. Basically, if TrustZone SW is used, the Cortex-A
* cores and peripherals the TZ SW will use should be in a secure partition. Almost all
* other partitions (for a non-secure OS or M4 cores) should be in non-secure partitions.
*
* Isolated should be true for almost all partitions. The exception is the non-secure
* partition for a Cortex-A core used to run a non-secure OS. This isn't isolated by
* domain but is instead isolated by the TZ security hardware.
*
* If restricted then the new partition is limited in what functions it can call,
* especially those associated with managing partitions.
*
* The grant option is usually used to isolate a bus master's traffic to specific
* memory without isolating the peripheral interface of the master or the API
* controls of that master.
* controls of that master. This is only used when creating a sub-partition with
* no CPU. It's useful to separate out a master and the memory it uses.
*/
sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
sc_bool_t isolated, sc_bool_t restricted,
......@@ -316,6 +325,12 @@ sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
* assigned
* @param[in] resource resource to assign
*
* This function assigned a resource to a partition. This partition is then
* the owner. All resources always have an owner (one owner). The owner
* has various rights to make API calls affecting the resource. Ownership
* does not imply access to the peripheral itself (that is based on access
* rights).
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* This action resets the resource's master and peripheral attributes.
......@@ -365,6 +380,12 @@ sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
* @param[in] resource resource to use to identify subsystem
* @param[in] movable movable flag (SC_TRUE is movable)
*
* A subsystem is a physical grouping within the chip of related resources;
* this is SoC specific. This function is used to optimize moving resource
* for these groupings, for instance, an M4 core and its associated resources.
* The list of subsystems and associated resources can be found in the
* SoC-specific API document [Resources](@ref RESOURCES) chapter.
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
......@@ -394,9 +415,13 @@ sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
* - SC_ERR_NOACCESS if caller's partition is not a parent of the resource owner,
* - SC_ERR_LOCKED if the owning partition is locked
*
* This function configures how the HW isolation will see bus transactions
* from the specified master. Note the security attribute will only be
* changed if the caller's partition is secure.
* Masters are IP blocks that generate bus transactions. This function configures
* how the isolation HW will define these bus transactions from the specified master.
* Note the security attribute will only be changed if the caller's partition is
* secure.
*
* Note an IP block can be both a master and peripheral (have both a programming model
* and generate bus transactions).
*/
sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rm_spa_t sa, sc_rm_spa_t pa,
......@@ -443,9 +468,15 @@ sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource,
* - SC_ERR_LOCKED if the owning partition is locked
* - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt
*
* This function configures how the HW isolation will restrict access to a
* Peripherals are IP blocks that have a programming model that can be
* accessed.
*
* This function configures how the isolation HW will restrict access to a
* peripheral based on the attributes of a transaction from bus master. It
* also allows the access permissions of SC_R_SYSTEM to be set.
*
* Note an IP block can be both a master and peripheral (have both a programming
* model and generate bus transactions).
*/
sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rm_pt_t pt, sc_rm_perm_t perm);
......@@ -485,6 +516,10 @@ sc_err_t sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource,
* @param[in] ipc IPC handle
* @param[in] resource resource to check
*
* Masters are IP blocks that generate bus transactions. Note an IP block
* can be both a master and peripheral (have both a programming model
* and generate bus transactions).
*
* @return Returns a boolean (SC_TRUE if the resource is a bus master).
*
* If \a resource is out of range then SC_FALSE is returned.
......@@ -497,6 +532,10 @@ sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource);
* @param[in] ipc IPC handle
* @param[in] resource resource to check
*
* Peripherals are IP blocks that have a programming model that can be
* accessed. Note an IP block can be both a master and peripheral (have
* both a programming model and generate bus transactions)
*
* @return Returns a boolean (SC_TRUE if the resource is a peripheral).
*
* If \a resource is out of range then SC_FALSE is returned.
......@@ -676,6 +715,12 @@ sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr);
* applied for
* @param[in] perm permissions to apply to \a mr for \a pt
*
* This function assigned a memory region to a partition. This partition is then
* the owner. All regions always have an owner (one owner). The owner
* has various rights to make API calls affecting the region. Ownership
* does not imply access to the memory itself (that is based on access
* rights).
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
......@@ -754,6 +799,10 @@ sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
* @param[in] pad_lst last pad for which flag should be set
* @param[in] movable movable flag (SC_TRUE is movable)
*
* This function assigned a pad to a partition. This partition is then
* the owner. All pads always have an owner (one owner). The owner
* has various rights to make API calls affecting the pad.
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
......
include/soc/imx8/sc/svc/seco/api.h
+ 50
− 0
View file @ ea1f1437
......@@ -38,6 +38,15 @@
#define SC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */
/*@}*/
/*!
* @name Defines for seco_rng_stat_t
*/
/*@{*/
#define SC_SECO_RNG_STAT_UNAVAILABLE 0U /* Unable to initialize the RNG */
#define SC_SECO_RNG_STAT_INPROGRESS 1U /* Initialization is on-going */
#define SC_SECO_RNG_STAT_READY 2U /* Initialized */
/*@}*/
/* Types */
/*!
......@@ -45,6 +54,11 @@
*/
typedef uint8_t sc_seco_auth_cmd_t;
/*!
* This type is used to return the RNG initialization status.
*/
typedef uint32_t sc_seco_rng_stat_t;
/* Functions */
/*!
......@@ -504,6 +518,42 @@ sc_err_t sc_seco_get_event(sc_ipc_t ipc, uint8_t idx, uint32_t *event);
*/
sc_err_t sc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr);
/*!
* This function applies a patch.
*
* @param[in] ipc IPC handle
* @param[in] addr address of message block
*
* @return Returns and error code (SC_ERR_NONE = success).
*
* Return errors codes:
* - SC_ERR_UNAVAILABLE if SECO not available
*
* Note \a addr must be a pointer to a signed message block.
*
* See the Security Reference Manual (SRM) for more info.
*/
sc_err_t sc_seco_patch(sc_ipc_t ipc, sc_faddr_t addr);
/*!
* This function starts the random number generator.
*
* @param[in] ipc IPC handle
* @param[out] status pointer to return state of RNG
*
* @return Returns and error code (SC_ERR_NONE = success).
*
* Return errors codes:
* - SC_ERR_UNAVAILABLE if SECO not available
*
* The RNG is started automatically after all CPUs are booted. This
* function can be used to start earlier and to check the status.
*
* See the Security Reference Manual (SRM) for more info.
*/
sc_err_t sc_seco_start_rng(sc_ipc_t ipc, sc_seco_rng_stat_t *status);
/* @} */
#endif /* SC_SECO_API_H */
......
include/soc/imx8/sc/types.h
+ 74
− 73
View file @ ea1f1437
......@@ -24,78 +24,79 @@
* @name Defines for common frequencies
*/
/*@{*/
#define SC_32KHZ 32768U /* 32KHz */
#define SC_10MHZ 10000000U /* 10MHz */
#define SC_20MHZ 20000000U /* 20MHz */
#define SC_25MHZ 25000000U /* 25MHz */
#define SC_27MHZ 27000000U /* 27MHz */
#define SC_40MHZ 40000000U /* 40MHz */
#define SC_45MHZ 45000000U /* 45MHz */
#define SC_50MHZ 50000000U /* 50MHz */
#define SC_60MHZ 60000000U /* 60MHz */
#define SC_66MHZ 66666666U /* 66MHz */
#define SC_74MHZ 74250000U /* 74.25MHz */
#define SC_80MHZ 80000000U /* 80MHz */
#define SC_83MHZ 83333333U /* 83MHz */
#define SC_84MHZ 84375000U /* 84.37MHz */
#define SC_100MHZ 100000000U /* 100MHz */
#define SC_125MHZ 125000000U /* 125MHz */
#define SC_133MHZ 133333333U /* 133MHz */
#define SC_135MHZ 135000000U /* 135MHz */
#define SC_150MHZ 150000000U /* 150MHz */
#define SC_160MHZ 160000000U /* 160MHz */
#define SC_166MHZ 166666666U /* 166MHz */
#define SC_175MHZ 175000000U /* 175MHz */
#define SC_180MHZ 180000000U /* 180MHz */
#define SC_200MHZ 200000000U /* 200MHz */
#define SC_250MHZ 250000000U /* 250MHz */
#define SC_266MHZ 266666666U /* 266MHz */
#define SC_300MHZ 300000000U /* 300MHz */
#define SC_312MHZ 312500000U /* 312.5MHZ */
#define SC_320MHZ 320000000U /* 320MHz */
#define SC_325MHZ 325000000U /* 325MHz */
#define SC_333MHZ 333333333U /* 333MHz */
#define SC_350MHZ 350000000U /* 350MHz */
#define SC_372MHZ 372000000U /* 372MHz */
#define SC_375MHZ 375000000U /* 375MHz */
#define SC_400MHZ 400000000U /* 400MHz */
#define SC_500MHZ 500000000U /* 500MHz */
#define SC_594MHZ 594000000U /* 594MHz */
#define SC_625MHZ 625000000U /* 625MHz */
#define SC_640MHZ 640000000U /* 640MHz */
#define SC_648MHZ 648000000U /* 648MHz */
#define SC_650MHZ 650000000U /* 650MHz */
#define SC_667MHZ 666666667U /* 667MHz */
#define SC_675MHZ 675000000U /* 675MHz */
#define SC_700MHZ 700000000U /* 700MHz */
#define SC_720MHZ 720000000U /* 720MHz */
#define SC_750MHZ 750000000U /* 750MHz */
#define SC_753MHZ 753000000U /* 753MHz */
#define SC_793MHZ 793000000U /* 793MHz */
#define SC_800MHZ 800000000U /* 800MHz */
#define SC_850MHZ 850000000U /* 850MHz */
#define SC_858MHZ 858000000U /* 858MHz */
#define SC_900MHZ 900000000U /* 900MHz */
#define SC_953MHZ 953000000U /* 953MHz */
#define SC_963MHZ 963000000U /* 963MHz */
#define SC_1000MHZ 1000000000U /* 1GHz */
#define SC_1060MHZ 1060000000U /* 1.06GHz */
#define SC_1068MHZ 1068000000U /* 1.068GHz */
#define SC_1121MHZ 1121000000U /* 1.121GHz */
#define SC_1173MHZ 1173000000U /* 1.173GHz */
#define SC_1188MHZ 1188000000U /* 1.188GHz */
#define SC_1260MHZ 1260000000U /* 1.26GHz */
#define SC_1278MHZ 1278000000U /* 1.278GHz */
#define SC_1280MHZ 1280000000U /* 1.28GHz */
#define SC_1300MHZ 1300000000U /* 1.3GHz */
#define SC_1313MHZ 1313000000U /* 1.313GHz */
#define SC_1345MHZ 1345000000U /* 1.345GHz */
#define SC_1400MHZ 1400000000U /* 1.4GHz */
#define SC_1500MHZ 1500000000U /* 1.5GHz */
#define SC_1600MHZ 1600000000U /* 1.6GHz */
#define SC_1800MHZ 1800000000U /* 1.8GHz */
#define SC_2000MHZ 2000000000U /* 2.0GHz */
#define SC_2112MHZ 2112000000U /* 2.12GHz */
#define SC_32KHZ 32768U /* 32KHz */
#define SC_10MHZ 10000000U /* 10MHz */
#define SC_16MHZ 16000000U /* 16MHz */
#define SC_20MHZ 20000000U /* 20MHz */
#define SC_25MHZ 25000000U /* 25MHz */
#define SC_27MHZ 27000000U /* 27MHz */
#define SC_40MHZ 40000000U /* 40MHz */
#define SC_45MHZ 45000000U /* 45MHz */
#define SC_50MHZ 50000000U /* 50MHz */
#define SC_60MHZ 60000000U /* 60MHz */
#define SC_66MHZ 66666666U /* 66MHz */
#define SC_74MHZ 74250000U /* 74.25MHz */
#define SC_80MHZ 80000000U /* 80MHz */
#define SC_83MHZ 83333333U /* 83MHz */
#define SC_84MHZ 84375000U /* 84.37MHz */
#define SC_100MHZ 100000000U /* 100MHz */
#define SC_125MHZ 125000000U /* 125MHz */
#define SC_133MHZ 133333333U /* 133MHz */
#define SC_135MHZ 135000000U /* 135MHz */
#define SC_150MHZ 150000000U /* 150MHz */
#define SC_160MHZ 160000000U /* 160MHz */
#define SC_166MHZ 166666666U /* 166MHz */
#define SC_175MHZ 175000000U /* 175MHz */
#define SC_180MHZ 180000000U /* 180MHz */
#define SC_200MHZ 200000000U /* 200MHz */
#define SC_250MHZ 250000000U /* 250MHz */
#define SC_266MHZ 266666666U /* 266MHz */
#define SC_300MHZ 300000000U /* 300MHz */
#define SC_312MHZ 312500000U /* 312.5MHZ */
#define SC_320MHZ 320000000U /* 320MHz */
#define SC_325MHZ 325000000U /* 325MHz */
#define SC_333MHZ 333333333U /* 333MHz */
#define SC_350MHZ 350000000U /* 350MHz */
#define SC_372MHZ 372000000U /* 372MHz */
#define SC_375MHZ 375000000U /* 375MHz */
#define SC_400MHZ 400000000U /* 400MHz */
#define SC_500MHZ 500000000U /* 500MHz */
#define SC_594MHZ 594000000U /* 594MHz */
#define SC_625MHZ 625000000U /* 625MHz */
#define SC_640MHZ 640000000U /* 640MHz */
#define SC_648MHZ 648000000U /* 648MHz */
#define SC_650MHZ 650000000U /* 650MHz */
#define SC_667MHZ 666666667U /* 667MHz */
#define SC_675MHZ 675000000U /* 675MHz */
#define SC_700MHZ 700000000U /* 700MHz */
#define SC_720MHZ 720000000U /* 720MHz */
#define SC_750MHZ 750000000U /* 750MHz */
#define SC_753MHZ 753000000U /* 753MHz */
#define SC_793MHZ 793000000U /* 793MHz */
#define SC_800MHZ 800000000U /* 800MHz */
#define SC_850MHZ 850000000U /* 850MHz */
#define SC_858MHZ 858000000U /* 858MHz */
#define SC_900MHZ 900000000U /* 900MHz */
#define SC_953MHZ 953000000U /* 953MHz */
#define SC_963MHZ 963000000U /* 963MHz */
#define SC_1000MHZ 1000000000U /* 1GHz */
#define SC_1060MHZ 1060000000U /* 1.06GHz */
#define SC_1068MHZ 1068000000U /* 1.068GHz */
#define SC_1121MHZ 1121000000U /* 1.121GHz */
#define SC_1173MHZ 1173000000U /* 1.173GHz */
#define SC_1188MHZ 1188000000U /* 1.188GHz */
#define SC_1260MHZ 1260000000U /* 1.26GHz */
#define SC_1278MHZ 1278000000U /* 1.278GHz */
#define SC_1280MHZ 1280000000U /* 1.28GHz */
#define SC_1300MHZ 1300000000U /* 1.3GHz */
#define SC_1313MHZ 1313000000U /* 1.313GHz */
#define SC_1345MHZ 1345000000U /* 1.345GHz */
#define SC_1400MHZ 1400000000U /* 1.4GHz */
#define SC_1500MHZ 1500000000U /* 1.5GHz */
#define SC_1600MHZ 1600000000U /* 1.6GHz */
#define SC_1800MHZ 1800000000U /* 1.8GHz */
#define SC_2000MHZ 2000000000U /* 2.0GHz */
#define SC_2112MHZ 2112000000U /* 2.12GHz */
/*@}*/
/*!
......@@ -205,7 +206,7 @@
#define SC_R_DC_0_BLIT2 21U
#define SC_R_DC_0_BLIT_OUT 22U
#define SC_R_PERF 23U
#define SC_R_UNUSED5 24U
#define SC_R_USB_1_PHY 24U
#define SC_R_DC_0_WARP 25U
#define SC_R_UNUSED7 26U
#define SC_R_UNUSED8 27U
......
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