MIPS: OCTEON: More OCTEONIII support
Read clock rate from the correct CSR. Don't clear COP0_DCACHE for OCTEONIII. Signed-off-by:Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by:
Aleksey Makarov <aleksey.makarov@auriga.com> Signed-off-by:
David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8945/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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- arch/mips/cavium-octeon/csrc-octeon.c 10 additions, 1 deletionarch/mips/cavium-octeon/csrc-octeon.c
- arch/mips/cavium-octeon/setup.c 7 additions, 1 deletionarch/mips/cavium-octeon/setup.c
- arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 3 additions, 0 deletionsarch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
- arch/mips/include/asm/octeon/cvmx-rst-defs.h 306 additions, 0 deletionsarch/mips/include/asm/octeon/cvmx-rst-defs.h
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