[C61][DTO][EDP] Fix edp backlight's signals order and timings
The current configuration of the backlight can create problem with some panels; the new correct sequence is: 1) VCC_BKL_EN (pca6416_20 9) - wait 40 ms 2) PWM start - wait 10 ms 3) iMX8_LVDS_BKL_ON (gpio4 4)
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mentioned in commit clea-os/layers/seco/meta-seco-imx@0e7dbd2e
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mentioned in merge request clea-os/layers/seco/meta-seco-imx!512 (merged)
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mentioned in commit clea-os/seco-manifest@2afab4c0
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mentioned in commit clea-os/layers/seco/meta-seco-imx@4230b920
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mentioned in commit clea-os/seco-manifest@641e508b
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mentioned in merge request clea-os/seco-manifest!831 (merged)