LF-4227-3 ARM: dts: change the spi-nor tx/rx

Before commit 0e30f472 ("mtd: spi-nor: add support for DTR protocol"),
for all PP command, it only support 1-1-1 mode, no matter the tx setting
in dts. But after the upper commit, the logic change. It will choose
the best mode(fastest mode) which flash device and spi-nor host controller
both support.
Though the spi-nor device on imx6sx-sdb/imx6ul(l/z)-14x14-evk/imx7d-sdb board
do not support PP-1-4-4, but if tx is 4 in dts file, it will also impact the
read mode select. For the spi-nor on the upper mentioned boards, it support
read 1-4-4 mode and read 1-1-4 mode in sfdp register. But according to test,
this read 1-4-4 mode do not stable enough. So set the tx to 1 in dts, let the
common code finally select read 1-1-4 mode, which can work stable enough.

Acked-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

arch/arm/boot/dts/imx6sx-sdb.dts

@@ -131,7 +131,7 @@
 		compatible = "micron,n25q256a", "jedec,spi-nor";
 		spi-max-frequency = <29000000>;
 		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
 		reg = <0>;
 	};
 
@@ -141,7 +141,7 @@
 		compatible = "micron,n25q256a", "jedec,spi-nor";
 		spi-max-frequency = <29000000>;
 		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
 		reg = <2>;
 	};
 };

arch/arm/boot/dts/imx6ul-14x14-evk.dtsi

@@ -347,7 +347,7 @@
 		compatible = "micron,n25q256a", "jedec,spi-nor";
 		spi-max-frequency = <29000000>;
 		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
 		reg = <0>;
 	};
 };

arch/arm/boot/dts/imx7d-sdb-qspi.dtsi

@@ -38,7 +38,7 @@
 		compatible = "jedec,spi-nor";
 		spi-max-frequency = <29000000>;
 		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
 		reg = <0>;
 	};
 };