MLK-16538-3: hdmi/dp: Add imx8qm hdmi/dp driver

Add hdmi/dp drm architecture driver.
HDMI and DP driver can work in imx8qm ARM2 board.
The driver support basic hotplug function.
Default working mode is 1080p60.

Acked-by: Robby Cai <robby.cai@nxp.com>
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
(Vipul: Fixed merge conflicts)
Signed-off-by: Vipul Kumar <vipul_kumar@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>

drivers/gpu/drm/imx/hdp/API_AFE_mcu1_dp.c

+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Copyright 2017 NXP
+ *
+ ******************************************************************************
+ *
+ * API_AFE_mcu1_dp.c
+ *
+ ******************************************************************************
+ */
+
+#include <linux/delay.h>
+#include "API_AFE_mcu1_dp.h"
+#include "../../../../mxc/hdp/all.h"
+
+static void AFE_WriteReg(state_struct *state, ENUM_AFE_LINK_RATE link_rate,
+				u32 addr, u32 val1_6, u32 val2_7, u32 val5_4)
+{
+	switch (link_rate) {
+	case AFE_LINK_RATE_1_6:
+		Afe_write(state, addr, val1_6);
+		break;
+
+	case AFE_LINK_RATE_2_7:
+		Afe_write(state, addr, val2_7);
+		break;
+
+	case AFE_LINK_RATE_5_4:
+		Afe_write(state, addr, val5_4);
+		break;
+
+	case AFE_LINK_RATE_8_1:	/* Not used in MCU1 */
+	default:
+		pr_err("Warning. Unsupported Link Rate!\n");
+		break;
+	}
+}
+
+void phy_cfg_24mhz(state_struct *state, int num_lanes)
+{
+	int k;
+
+	for (k = 0; k < num_lanes; k++) {
+		Afe_write(state, XCVR_DIAG_LANE_FCM_EN_MGN_TMR | (k << 9), 0x0090);
+		Afe_write(state, TX_RCVDET_EN_TMR | (k << 9), 0x0960);
+		Afe_write(state, TX_RCVDET_ST_TMR | (k << 9), 0x0030);
+	}
+}
+
+/* Valid for 24 MHz only */
+void phy_cfg_dp_cmn_pll0(state_struct *state, int num_lanes)
+{
+	int k;
+	volatile u16 rdata;
+
+	Afe_write(state, PHY_HDP_CLK_CTL, 0x2405);
+	Afe_write(state, CMN_PLL0_INTDIV, 0x0086);
+	Afe_write(state, CMN_PLL0_FRACDIV, 0xF915);
+	Afe_write(state, CMN_PLL0_HIGH_THR, 0x0022);
+	Afe_write(state, CMN_PLL0_SS_CTRL1, 0x0140);
+	rdata = Afe_read(state, CMN_DIAG_HSCLK_SEL);
+	rdata = rdata & 0xFFFC;
+	rdata = rdata | 0x0001;
+	Afe_write(state, CMN_DIAG_HSCLK_SEL, rdata);
+	for (k = 0; k < num_lanes; k = k + 1) {
+		rdata = Afe_read(state, (XCVR_DIAG_HSCLK_SEL | (k << 9)));
+		rdata = rdata & 0xCFFF;
+		rdata = rdata | 0x1000;
+		Afe_write(state, (XCVR_DIAG_HSCLK_SEL | (k << 9)), rdata);
+	}
+	Afe_write(state, CMN_PLL0_VCOCAL_START, 0x3061);
+	Afe_write(state, CMN_PLLSM0_USER_DEF_CTRL, 0x0000);
+	Afe_write(state, CMN_DIAG_PLL0_V2I_TUNE, 0x0006);
+	Afe_write(state, CMN_DIAG_PLL0_PTATIS_TUNE1, 0x008c);
+	Afe_write(state, CMN_DIAG_PLL0_PTATIS_TUNE2, 0x002e);
+	Afe_write(state, CMN_DIAG_PLL0_CP_TUNE, 0x0026);
+	Afe_write(state, CMN_DIAG_PLL0_LF_PROG, 0x0008);
+	Afe_write(state, CMN_PLL0_VCOCAL_INIT_TMR, 0x00F0);
+	Afe_write(state, CMN_PLL0_VCOCAL_ITER_TMR, 0x0018);
+	Afe_write(state, CMN_PLL0_SS_CTRL2, 0x7F03);
+	Afe_write(state, CMN_PLL0_DSM_DIAG, 0x0020);
+	Afe_write(state, CMN_DIAG_PLL0_OVRD, 0x0000);
+	Afe_write(state, CMN_DIAG_PLL0_FBH_OVRD, 0x0000);
+	Afe_write(state, CMN_DIAG_PLL0_FBL_OVRD, 0x0000);
+}
+
+/* Valid for 24 MHz only */
+void phy_cfg_dp_pll0(state_struct *state, int num_lanes, ENUM_AFE_LINK_RATE link_rate)
+{
+	int k;
+	volatile u16 rdata;
+
+	rdata = Afe_read(state, PHY_HDP_CLK_CTL);
+	rdata = rdata & 0x00FF;
+
+	switch (link_rate) {
+	case AFE_LINK_RATE_1_6:
+	case AFE_LINK_RATE_2_7:
+		rdata = rdata | 0x2400;
+		break;
+
+	case AFE_LINK_RATE_5_4:
+		rdata = rdata | 0x1200;
+		break;
+
+	case AFE_LINK_RATE_8_1:	/* nNot used in MCU1 */
+	default:
+		pr_err("Warning. Unsupported Link Rate!\n");
+		break;
+	}
+
+	Afe_write(state, PHY_HDP_CLK_CTL, rdata);
+	rdata = Afe_read(state, CMN_DIAG_HSCLK_SEL);
+	rdata = rdata & 0xFFCC;
+	switch (link_rate) {
+	case AFE_LINK_RATE_1_6:
+	case AFE_LINK_RATE_2_7:
+		rdata = rdata | 0x0011;
+		break;
+
+	case AFE_LINK_RATE_5_4:
+		rdata = rdata | 0x0000;
+		break;
+
+	case AFE_LINK_RATE_8_1:	/* Not used in MCU1 */
+	default:
+		pr_err("Warning. Unsupported Link Rate!\n");
+		break;
+	}
+	Afe_write(state, CMN_DIAG_HSCLK_SEL, rdata);
+	for (k = 0; k < num_lanes; k = k + 1) {
+		rdata = Afe_read(state, (XCVR_DIAG_HSCLK_SEL | (k << 9)));
+		rdata = rdata & 0xCFFF;
+		switch (link_rate) {
+		case AFE_LINK_RATE_1_6:
+		case AFE_LINK_RATE_2_7:
+			rdata = rdata | 0x1000;
+			break;
+
+		case AFE_LINK_RATE_5_4:
+			rdata = rdata | 0x0000;
+			break;
+
+		case AFE_LINK_RATE_8_1:	/* Not used in MCU1 */
+		default:
+			pr_err("Warning. Unsupported Link Rate!\n");
+			break;
+		}
+		Afe_write(state, (XCVR_DIAG_HSCLK_SEL | (k << 9)), rdata);
+	}
+	AFE_WriteReg(state, link_rate, CMN_PLL0_VCOCAL_START, 0x3061, 0x30D0, 0x30D0);
+	AFE_WriteReg(state, link_rate, CMN_PLLSM0_USER_DEF_CTRL, 0x0000, 0x1000,
+		     0x1000);
+	AFE_WriteReg(state, link_rate, CMN_DIAG_PLL0_V2I_TUNE, 0x0006, 0x0007, 0x0007);
+	Afe_write(state, CMN_DIAG_PLL0_PTATIS_TUNE1, 0x008C);
+	Afe_write(state, CMN_DIAG_PLL0_PTATIS_TUNE2, 0x002E);
+	AFE_WriteReg(state, link_rate, CMN_DIAG_PLL0_CP_TUNE, 0x0026, 0x0029, 0x0029);
+	Afe_write(state, CMN_DIAG_PLL0_LF_PROG, 0x0008);
+	Afe_write(state, CMN_PLL0_VCOCAL_INIT_TMR, 0x00F0);
+	Afe_write(state, CMN_PLL0_VCOCAL_ITER_TMR, 0x0018);
+	AFE_WriteReg(state, link_rate, CMN_PLL0_INTDIV, 0x0086, 0x00E0, 0x00E0);
+	AFE_WriteReg(state, link_rate, CMN_PLL0_FRACDIV, 0xF915, 0xF479, 0xF479);
+	AFE_WriteReg(state, link_rate, CMN_PLL0_HIGH_THR, 0x0022, 0x0038, 0x0038);
+	AFE_WriteReg(state, link_rate, CMN_PLL0_SS_CTRL1, 0x0140, 0x0204, 0x0204);
+	Afe_write(state, CMN_PLL0_SS_CTRL2, 0x7F03);
+	Afe_write(state, CMN_PLL0_DSM_DIAG, 0x0020);
+	Afe_write(state, CMN_DIAG_PLL0_OVRD, 0x0000);
+	Afe_write(state, CMN_DIAG_PLL0_FBH_OVRD, 0x0000);
+	Afe_write(state, CMN_DIAG_PLL0_FBL_OVRD, 0x0000);
+	for (k = 0; k < num_lanes; k = k + 1) {
+		rdata = Afe_read(state, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)));
+		rdata = rdata & 0x8FFF;
+		switch (link_rate) {
+		case AFE_LINK_RATE_1_6:
+		case AFE_LINK_RATE_2_7:
+			rdata = rdata | 0x2000;
+			break;
+
+		case AFE_LINK_RATE_5_4:
+			rdata = rdata | 0x1000;
+			break;
+
+		case AFE_LINK_RATE_8_1:	/* Not used in MCU1 */
+		default:
+			pr_err("Warning. Unsupported Link Rate!\n");
+			break;
+		}
+		Afe_write(state, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)), rdata);
+	}
+}
+
+void phy_cfg_dp_ln(state_struct *state, int num_lanes)
+{
+	int k;
+	for (k = 0; k < num_lanes; k = k + 1) {
+		Afe_write(state, (XCVR_PSM_RCTRL | (k << 9)), 0xBEFC);
+		Afe_write(state, (TX_PSC_A0 | (k << 9)), 0x6799);
+		Afe_write(state, (TX_PSC_A1 | (k << 9)), 0x6798);
+		Afe_write(state, (TX_PSC_A2 | (k << 9)), 0x0098);
+		Afe_write(state, (TX_PSC_A3 | (k << 9)), 0x0098);
+	}
+}
+
+u16 aux_cal_cfg(state_struct *state, u16 prev_calib_code)
+{
+	u16 txpu_calib_code;
+	u16 txpd_calib_code;
+	u16 txpu_adj_calib_code;
+	u16 txpd_adj_calib_code;
+	u16 new_calib_code;
+	u16 rdata;
+
+	txpu_calib_code = Afe_read(state, CMN_TXPUCAL_CTRL);
+	txpd_calib_code = Afe_read(state, CMN_TXPDCAL_CTRL);
+	txpu_adj_calib_code = Afe_read(state, CMN_TXPU_ADJ_CTRL);
+	txpd_adj_calib_code = Afe_read(state, CMN_TXPD_ADJ_CTRL);
+
+	new_calib_code = ((txpu_calib_code + txpd_calib_code) / 2)
+	    + txpu_adj_calib_code + txpd_adj_calib_code;
+
+	if (new_calib_code != prev_calib_code) {
+		rdata = Afe_read(state, TX_ANA_CTRL_REG_1);
+		rdata &= 0xDFFF;
+		Afe_write(state, TX_ANA_CTRL_REG_1, rdata);
+		Afe_write(state, TX_DIG_CTRL_REG_2, new_calib_code);
+		udelay(10000);
+		rdata |= 0x2000;
+		Afe_write(state, TX_ANA_CTRL_REG_1, rdata);
+		udelay(150);
+	}
+
+	return new_calib_code;
+}
+
+void aux_cfg(state_struct *state)
+{
+	volatile u16 rdata;
+
+	Afe_write(state, TX_DIG_CTRL_REG_2, 36);
+
+	Afe_write(state, TX_ANA_CTRL_REG_2, 0x0100);
+	udelay(150);
+	Afe_write(state, TX_ANA_CTRL_REG_2, 0x0300);
+	udelay(150);
+	Afe_write(state, TX_ANA_CTRL_REG_3, 0x0000);
+	udelay(150);
+	Afe_write(state, TX_ANA_CTRL_REG_1, 0x2008);
+	udelay(150);
+	Afe_write(state, TX_ANA_CTRL_REG_1, 0x2018);
+	udelay(150);
+	Afe_write(state, TX_ANA_CTRL_REG_1, 0xA018);
+	udelay(150);
+	Afe_write(state, TX_ANA_CTRL_REG_2, 0x030C);
+	udelay(150);
+	Afe_write(state, TX_ANA_CTRL_REG_5, 0x0000);
+	udelay(150);
+	Afe_write(state, TX_ANA_CTRL_REG_4, 0x1001);
+	udelay(150);
+	Afe_write(state, TX_ANA_CTRL_REG_1, 0xA098);
+	udelay(5000);
+	Afe_write(state, TX_ANA_CTRL_REG_1, 0xA198);
+	udelay(5000);
+	Afe_write(state, TX_ANA_CTRL_REG_2, 0x030D);
+	udelay(5000);
+	Afe_write(state, TX_ANA_CTRL_REG_2, 0x030F);
+	udelay(5000);
+
+	pr_info("TX_ANA_CTRL_REG_1 %x)\n", rdata);
+	rdata = Afe_read(state, TX_ANA_CTRL_REG_2);
+	pr_info("TX_ANA_CTRL_REG_2 %x)\n", rdata);
+	rdata = Afe_read(state, TX_ANA_CTRL_REG_3);
+	pr_info("TX_ANA_CTRL_REG_3 %x)\n", rdata);
+	rdata = Afe_read(state, TX_ANA_CTRL_REG_4);
+	pr_info("TX_ANA_CTRL_REG_4 %x)\n", rdata);
+	rdata = Afe_read(state, TX_ANA_CTRL_REG_5);
+	pr_info("TX_ANA_CTRL_REG_5 %x)\n", rdata);
+}
+
+void AFE_init(state_struct *state, int num_lanes, ENUM_AFE_LINK_RATE link_rate)
+{
+	volatile u16 val;
+
+	val = Afe_read(state, PHY_PMA_CMN_CTRL1);
+	val = val & 0xFFF7;
+	val = val | 0x0008;
+	Afe_write(state, PHY_PMA_CMN_CTRL1, val);
+
+	Afe_write(state, CMN_DIAG_PLL0_TEST_MODE, 0x0020);
+	Afe_write(state, CMN_PSM_CLK_CTRL, 0x0016);
+
+	phy_cfg_24mhz(state, num_lanes);
+
+	phy_cfg_dp_pll0(state, num_lanes, link_rate);
+
+	val = Afe_read(state, PHY_PMA_CMN_CTRL1);
+	val = val & 0xFF8F;
+	val = val | 0x0030;
+	Afe_write(state, PHY_PMA_CMN_CTRL1, val);
+
+	phy_cfg_dp_ln(state, num_lanes);
+
+	/* Configure PHY in A2 Mode */
+	Afe_write(state, PHY_HDP_MODE_CTRL, 0x0004);
+
+}
+
+void AFE_power(state_struct *state, int num_lanes, ENUM_AFE_LINK_RATE link_rate)
+{
+	static u16 prev_calib_code;
+
+	volatile u16 val;
+
+	Afe_write(state, TX_DIAG_ACYA_0, 1);
+	Afe_write(state, TX_DIAG_ACYA_1, 1);
+	Afe_write(state, TX_DIAG_ACYA_2, 1);
+	Afe_write(state, TX_DIAG_ACYA_3, 1);
+
+	Afe_write(state, TXDA_CYA_AUXDA_CYA, 1);
+
+	/* Wait for A2 ACK (PHY_HDP_MODE_CTL [6] = 1’b1) */
+	do {
+		val = Afe_read(state, PHY_HDP_MODE_CTRL);
+		val = val >> 6;
+	} while ((val & 1) == 0);
+
+	/* to check if PLL has locked (bit 6) */
+	val = Afe_read(state, PHY_PMA_CMN_CTRL2);
+	val = val >> 6;
+
+	if ((val & 1) == 0) {
+		pr_err("ERROR: PLL is not locked\n");
+	} else {
+		pr_info("PHY_PMA_CMN_CTRL2 = %x\n", val);
+	}
+
+	/* to check if cmn_ready is asserted (bit 0) */
+	val = Afe_read(state, PHY_PMA_CMN_CTRL1);
+
+	if ((val & 1) == 0) {
+		pr_err("ERROR: cmn_ready is not asserted\n");
+	} else {
+		pr_info("PHY_PMA_CMN_CTRL1 = %x\n", val);
+	}
+
+	/* Configure PHY in A0 mode (PHY must be in the A0 power state in order to transmit data) */
+	Afe_write(state, PHY_HDP_MODE_CTRL, 0x0101);
+
+	/* Wait for A2 ACK (PHY_HDP_MODE_CTL [4] = 1’b1) */
+	do {
+		val = Afe_read(state, PHY_HDP_MODE_CTRL);
+		val = val >> 4;
+	} while ((val & 1) == 0);
+
+	prev_calib_code = aux_cal_cfg(state, prev_calib_code);
+
+	aux_cfg(state);
+
+}

drivers/gpu/drm/imx/hdp/API_AFE_mcu1_dp.h

+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AFE_mcu1_dp.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_AFE_MCU1_DP_H
+# define API_AFE_MCU1_DP_H
+
+#define PHY_PMA_CMN_CTRL1 0xC800
+#define PHY_PMA_CMN_CTRL2 0xC801
+#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40F2
+#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR_0 0x40F2
+#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR_1 0x42F2
+#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR_2 0x44F2
+#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR_3 0x46F2
+#define TX_RCVDET_EN_TMR 0x4122
+#define TX_RCVDET_EN_TMR_0 0x4122
+#define TX_RCVDET_EN_TMR_1 0x4322
+#define TX_RCVDET_EN_TMR_2 0x4522
+#define TX_RCVDET_EN_TMR_3 0x4722
+#define TX_RCVDET_ST_TMR 0x4123
+#define TX_RCVDET_ST_TMR_0 0x4123
+#define TX_RCVDET_ST_TMR_1 0x4323
+#define TX_RCVDET_ST_TMR_2 0x4523
+#define TX_RCVDET_ST_TMR_3 0x4723
+#define PHY_HDP_CLK_CTL 0xC009
+#define CMN_DIAG_HSCLK_SEL 0x01E0
+#define XCVR_DIAG_HSCLK_SEL 0x40E1
+#define XCVR_DIAG_HSCLK_SEL_0 0x40E1
+#define XCVR_DIAG_HSCLK_SEL_1 0x42E1
+#define XCVR_DIAG_HSCLK_SEL_2 0x44E1
+#define XCVR_DIAG_HSCLK_SEL_3 0x46E1
+#define CMN_PLL0_VCOCAL_START 0x0081
+#define CMN_PLLSM0_USER_DEF_CTRL 0x002F
+#define CMN_DIAG_PLL0_V2I_TUNE 0x01C5
+#define CMN_DIAG_PLL0_PTATIS_TUNE1 0x01C8
+#define CMN_DIAG_PLL0_PTATIS_TUNE2 0x01C9
+#define CMN_DIAG_PLL0_CP_TUNE 0x01C6
+#define CMN_DIAG_PER_CAL_ADJ 0x01EC
+#define CMN_DIAG_PLL0_LF_PROG 0x01C7
+#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084
+#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085
+#define CMN_PLL0_INTDIV 0x0094
+#define CMN_PLL0_FRACDIV 0x0095
+#define CMN_PLL0_HIGH_THR 0x0096
+#define CMN_PLL0_SS_CTRL1 0x0098
+#define CMN_PLL0_SS_CTRL2 0x0099
+#define CMN_PLL0_DSM_DIAG 0x0097
+#define CMN_DIAG_PLL0_OVRD 0x01C2
+#define CMN_DIAG_PLL0_FBH_OVRD 0x01C0
+#define CMN_DIAG_PLL0_FBL_OVRD 0x01C1
+#define XCVR_DIAG_PLLDRC_CTRL 0x40E0
+#define XCVR_DIAG_PLLDRC_CTRL_0 0x40E0
+#define XCVR_DIAG_PLLDRC_CTRL_1 0x42E0
+#define XCVR_DIAG_PLLDRC_CTRL_2 0x44E0
+#define XCVR_DIAG_PLLDRC_CTRL_3 0x46E0
+#define CMN_DIAG_PLL0_TEST_MODE 0x01C4
+#define PHY_HDP_MODE_CTRL 0xC008
+#define XCVR_PSM_RCTRL 0x4001
+#define XCVR_PSM_RCTRL_0 0x4001
+#define XCVR_PSM_RCTRL_1 0x4201
+#define XCVR_PSM_RCTRL_2 0x4401
+#define XCVR_PSM_RCTRL_3 0x4601
+#define TX_PSC_A0 0x4100
+#define TX_PSC_A0_0 0x4100
+#define TX_PSC_A0_1 0x4300
+#define TX_PSC_A0_2 0x4500
+#define TX_PSC_A0_3 0x4700
+#define TX_PSC_A1 0x4101
+#define TX_PSC_A1_0 0x4101
+#define TX_PSC_A1_1 0x4301
+#define TX_PSC_A1_2 0x4501
+#define TX_PSC_A1_3 0x4701
+#define TX_PSC_A2 0x4102
+#define TX_PSC_A2_0 0x4102
+#define TX_PSC_A2_1 0x4302
+#define TX_PSC_A2_2 0x4502
+#define TX_PSC_A2_3 0x4702
+#define TX_PSC_A3 0x4103
+#define TX_PSC_A3_0 0x4103
+#define TX_PSC_A3_1 0x4303
+#define TX_PSC_A3_2 0x4503
+#define TX_PSC_A3_3 0x4703
+#define TX_DIAG_TX_DRV 0x41E1
+#define TX_DIAG_TX_DRV_0 0x41E1
+#define TX_DIAG_TX_DRV_1 0x43E1
+#define TX_DIAG_TX_DRV_2 0x45E1
+#define TX_DIAG_TX_DRV_3 0x47E1
+#define PHY_HDP_MODE CTRL 0xC008
+#define TX_DIAG_ACYA_0 0x41ff
+#define TX_DIAG_ACYA_1 0x43ff
+#define TX_DIAG_ACYA_2 0x45ff
+#define TX_DIAG_ACYA_3 0x47ff
+
+#define TX_TXCC_MGNFS_MULT_000_0 0x4050
+#define TX_TXCC_MGNFS_MULT_000_1 0x4250
+#define TX_TXCC_MGNFS_MULT_000_2 0x4450
+#define TX_TXCC_MGNFS_MULT_000_3 0x4650
+
+#define TX_TXCC_CPOST_MULT_00_0 0x404C
+#define TX_TXCC_CPOST_MULT_00_1 0x424C
+#define TX_TXCC_CPOST_MULT_00_2 0x444C
+#define TX_TXCC_CPOST_MULT_00_3 0x464C
+
+#define TX_ANA_CTRL_REG_1  0x5020
+#define TX_ANA_CTRL_REG_2  0x5021
+#define TX_ANA_CTRL_REG_3  0x5026
+#define TX_ANA_CTRL_REG_4  0x5027
+#define TX_ANA_CTRL_REG_5  0x5029
+
+#define TX_DIG_CTRL_REG_2  0x5024
+#define TX_DIG_CTRL_REG_1  0x5023
+#define TXDA_CYA_AUXDA_CYA 0x5025
+#define CMN_TXPUCAL_CTRL 0x00E0
+#define CMN_TXPDCAL_CTRL 0x00F0
+#define CMN_TXPU_ADJ_CTRL 0x0108
+#define CMN_TXPD_ADJ_CTRL 0x010c
+#define TXDA_COEFF_CALC 0x5022
+#define CMN_PSM_CLK_CTRL 0x0061
+
+#define PHY_HDP_TX_CTL_L0 0xC408
+#define PHY_HDP_TX_CTL_L1 0xC448
+#define PHY_HDP_TX_CTL_L2 0xC488
+#define PHY_HDP_TX_CTL_L3 0xC4C8
+
+#endif //API_AFE_MCU1_DP_H

drivers/gpu/drm/imx/hdp/API_AFE_ss28fdsoi_kiran_hdmitx.h

+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AFE_ss28fdsoi_kiran_hdmitx.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_AFE_SS28FDSOI_KIRAN_HDMITX_H_
+#define API_AFE_SS28FDSOI_KIRAN_HDMITX_H_
+
+#include "../../../../mxc/hdp/all.h"
+
+int phy_cfg_hdp_ss28fdsoi(state_struct *state, int num_lanes,
+				VIC_MODES vicMode, int bpp, VIC_PXL_ENCODING_FORMAT format);
+int hdmi_tx_kiran_power_configuration_seq(state_struct *state, int num_lanes);
+int get_table_row_match_column(const u32 *array, u32 table_rows,
+			       u32 table_cols, u32 start_row,
+			       u32 column_to_search,
+			       u32 value_to_search_in_column);
+int get_table_row(const u32 *array, u32 table_rows,
+		  u32 table_cols, u32 variable_in_range,
+		  u32 range_min_column, u32 range_max_column,
+		  u32 column_to_search, u32 column_value);
+
+#endif

drivers/gpu/drm/imx/hdp/Kconfig

+config DRM_IMX_HDP
+	tristate "IMX8 HD Display Controller"
+	select DRM_IMX
+	select MX8_HDP_DP
+	select DRM_KMS_HELPER
+	select VIDEOMODE_HELPERS
+	select DRM_GEM_CMA_HELPER
+	select DRM_KMS_CMA_HELPER
+	select DRM_PANEL
+	help
+	  Choose this if you want to use DP/HDMI on i.MX8.

drivers/gpu/drm/imx/hdp/Makefile

+obj-$(CONFIG_DRM_IMX_HDP) += imx-hdp.o \
+			imx-dp.o imx-hdmi.o \
+			API_AFE_ss28fdsoi_kiran_hdmitx.o \
+			ss28fdsoi_hdmitx_table.o \
+			API_AFE_mcu1_dp.o

drivers/gpu/drm/imx/hdp/hdmitx_firmware.h

+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated from dram0.data and iram0.data firmware images
+ * Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * hdmitx_firmware.c
+ *
+ ******************************************************************************
+ */
+#include <linux/io.h>
+
+static u32 const hdmitx_iram0[] = {
+    0x00000000,
+};
+
+static u32 const hdmitx_dram0[] = {
+    0x00000000,
+};
+
+u32 const *hdmitx_iram0_get_ptr(void)
+{
+    return (u32 const *)hdmitx_iram0;
+}
+
+u32 const *hdmitx_dram0_get_ptr(void)
+{
+    return (u32 const *)hdmitx_dram0;
+}
+
+size_t hdmitx_iram0_get_size(void)
+{
+    return sizeof(hdmitx_iram0);
+}
+
+size_t hdmitx_dram0_get_size(void)
+{
+    return sizeof(hdmitx_dram0);
+}

drivers/gpu/drm/imx/hdp/imx-dp.c

+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include "mhdp_firmware.h"
+#include "imx-hdp.h"
+#include "imx-hdmi.h"
+#include "imx-dp.h"
+
+void dp_fw_load(state_struct *state)
+{
+	printk("loading hdmi firmware\n");
+	CDN_API_LoadFirmware(state,
+		(u8 *)mhdp_iram0_get_ptr(),
+		mhdp_iram0_get_size(),
+		(u8 *)mhdp_dram0_get_ptr(),
+		mhdp_dram0_get_size());
+}
+
+void dp_fw_init(state_struct *state, u32 core_rate)
+{
+	u8 echo_msg[] = "echo test";
+	u8 echo_resp[sizeof(echo_msg) + 1];
+	int ret;
+	u8 resp;
+
+	/* configure the clock */
+	CDN_API_SetClock(state, core_rate/1000000);
+	printk("CDN_API_SetClock completed\n");
+
+	cdn_apb_write(state, APB_CTRL << 2, 0);
+	printk("Started firmware!\n");
+
+	ret = CDN_API_CheckAlive_blocking(state);
+	printk("CDN_API_CheckAlive returned (ret = %d)\n", ret);
+
+	/* turn on IP activity */
+	ret = CDN_API_MainControl_blocking(state, 1, &resp);
+	printk("CDN_API_MainControl_blocking (ret = %d resp = %u)\n",
+		ret, resp);
+
+	ret = CDN_API_General_Test_Echo_Ext_blocking(state, echo_msg, echo_resp,
+		sizeof(echo_msg), CDN_BUS_TYPE_APB);
+	printk("CDN_API_General_Test_Echo_Ext_blocking (ret = %d echo_resp = %s)\n",
+		ret, echo_resp);
+
+	/* Line swaping */
+	CDN_API_General_Write_Register_blocking(state,
+		ADDR_SOURCD_PHY + (LANES_CONFIG << 2), 0x0040001b);
+	printk("CDN_API_General_Write_Register_blockin ... setting LANES_CONFIG\n");
+}
+
+void dp_phy_init(state_struct *state, int num_lanes, int max_link_rate, int tmp)
+{
+	int ret;
+
+	/* PHY initialization while phy reset pin is active */
+	AFE_init(state, num_lanes, (ENUM_AFE_LINK_RATE)max_link_rate);
+	printk("AFE_init\n");
+
+	/* In this point the phy reset should be deactivated */
+	hdp_phy_reset(1);
+	printk("deasserted reset\n");
+
+	/* PHY power set */
+	AFE_power(state, num_lanes, (ENUM_AFE_LINK_RATE)max_link_rate);
+	printk("AFE_power exit\n");
+
+	/* Video off */
+	ret = CDN_API_DPTX_SetVideo_blocking(state, 0);
+	printk("CDN_API_DPTX_SetVideo_blocking (ret = %d)\n", ret);
+}
+
+/* Max Link Rate: 06h (1.62Gbps), 0Ah (2.7Gbps), 14h (5.4Gbps), 1Eh (8.1Gbps)--N/A */
+void dp_mode_set(state_struct *state, int vic, int format, int color_depth, int max_link_rate)
+{
+	int ret;
+
+	/* Set Host capabilities */
+	/* Number of lanes and SSC */
+	u8 num_lanes = 4;
+	u8 ssc = 0;
+	u8 scrambler = 0;
+	/* Max voltage swing */
+	u8 max_vswing = 3;
+	u8 force_max_vswing = 0;
+	/* Max pre-emphasis */
+	u8 max_preemph = 2;
+	u8 force_max_preemph = 0;
+	/* Supported test patterns mask */
+	u8 supp_test_patterns = 0x0F;
+	/* AUX training? */
+	u8 no_aux_training = 0;
+	/* Lane mapping */
+	u8 lane_mapping = 0x1B; /*  we have 4 lane, so it's OK */
+	/* Extended Host capabilities */
+	u8 ext_host_cap = 1;
+	/* Bits per sub-pixel */
+	u8 bits_per_subpixel = 8;
+	/* Stereoscopic video */
+	STEREO_VIDEO_ATTR stereo = 0;
+	/* B/W Balance Type: 0 no data, 1 IT601, 2 ITU709 */
+	BT_TYPE bt_type = 0;
+	/* Transfer Unit */
+	u8 transfer_unit = 64;
+	VIC_SYMBOL_RATE sym_rate;
+
+	ret = CDN_API_DPTX_SetHostCap_blocking(state,
+		max_link_rate,
+		(num_lanes & 0x7) | ((ssc & 1) << 3) | ((scrambler & 1) << 4),
+		(max_vswing & 0x3) | ((force_max_vswing & 1) << 4),
+		(max_preemph & 0x3) | ((force_max_preemph & 1) << 4),
+		supp_test_patterns,
+		no_aux_training, //fast link training
+		lane_mapping,
+		ext_host_cap
+		);
+	printk("CDN_API_DPTX_SetHostCap_blocking (ret = %d)\n", ret);
+
+	switch (max_link_rate) {
+	case 0x0a:
+		sym_rate = RATE_2_7;
+		break;
+	case 0x14:
+		sym_rate = RATE_5_4;
+		break;
+	default:
+		sym_rate = RATE_1_6;
+	}
+
+	ret = CDN_API_DPTX_Set_VIC_blocking(state,
+		vic,
+		bits_per_subpixel,
+		num_lanes,
+		sym_rate,
+		format,
+		stereo,
+		bt_type,
+		transfer_unit
+		);
+	printk("CDN_API_DPTX_Set_VIC_blocking (ret = %d)\n", ret);
+
+	ret = CDN_API_DPTX_TrainingControl_blocking(state, 1);
+	printk("CDN_API_DPTX_TrainingControl_blocking (ret = %d)\n", ret);
+
+	/* Set video on */
+	ret = CDN_API_DPTX_SetVideo_blocking(state, 1);
+	printk("CDN_API_DPTX_SetVideo_blocking (ret = %d)\n", ret);
+
+	udelay(1000);
+}
+
+int dp_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len)
+{
+    DPTX_Read_EDID_response edidResp;
+	state_struct *state = data;
+	CDN_API_STATUS ret = 0;
+
+	memset(&edidResp, 0, sizeof(edidResp));
+	switch (block) {
+	case 0:
+		ret = CDN_API_DPTX_Read_EDID_blocking(state, 0, 0, &edidResp);
+		break;
+	case 1:
+		ret = CDN_API_DPTX_Read_EDID_blocking(state, 0, 1, &edidResp);
+		break;
+	case 2:
+		ret = CDN_API_DPTX_Read_EDID_blocking(state, 1, 0, &edidResp);
+		break;
+	case 3:
+		ret = CDN_API_DPTX_Read_EDID_blocking(state, 1, 1, &edidResp);
+		break;
+	default:
+		pr_warn("EDID block %x read not support\n", block);
+	}
+
+	memcpy(buf, edidResp.buff, 128);
+
+	return ret;
+}
+
+void dp_get_hpd_state(state_struct *state, u8 *hpd)
+{
+	CDN_API_DPTX_GetHpdStatus_blocking(state, hpd);
+}

drivers/gpu/drm/imx/hdp/imx-dp.h

+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _IMX_DP_H_
+#define _IMX_DP_H_
+
+void dp_fw_load(state_struct *state);
+void dp_fw_init(state_struct *state, u32 rate);
+void dp_mode_set(state_struct *state, int vic, int format, int color_depth, int max_link_rate);
+void dp_phy_init(state_struct *state, int num_lanes, int max_link_rate, int tmp);
+int dp_get_edid_block(void *data, u8 *buf, u32 block, size_t len);
+void dp_get_hpd_state(state_struct *state, u8 *hpd);
+
+#endif

drivers/gpu/drm/imx/hdp/imx-hdmi.c

+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include "hdmitx_firmware.h"
+#include "imx-hdp.h"
+#include "imx-hdmi.h"
+#include "API_AFE_ss28fdsoi_kiran_hdmitx.h"
+
+static int character_freq_khz;
+
+void hdmi_fw_load(state_struct *state)
+{
+	printk("loading hdmi firmware\n");
+	CDN_API_LoadFirmware(state,
+		(u8 *)hdmitx_iram0_get_ptr(),
+		hdmitx_iram0_get_size(),
+		(u8 *)hdmitx_dram0_get_ptr(),
+		hdmitx_dram0_get_size());
+}
+
+void hdmi_fw_init(state_struct *state, u32 core_rate)
+{
+	u8 echo_msg[] = "echo test";
+	u8 echo_resp[sizeof(echo_msg) + 1];
+	int ret;
+	u8 sts;
+
+	/* configure the clock */
+	CDN_API_SetClock(state, core_rate/1000000);
+	printk("CDN_API_SetClock completed\n");
+
+	/* moved from CDN_API_LoadFirmware */
+	cdn_apb_write(state, APB_CTRL << 2, 0);
+	printk("Started firmware!\n");
+
+	ret = CDN_API_CheckAlive_blocking(state);
+	printk("CDN_API_CheckAlive returned ret = %d\n", ret);
+
+	/* turn on IP activity */
+	ret = CDN_API_MainControl_blocking(state, 1, &sts);
+	printk("CDN_API_MainControl_blocking ret = %d sts = %u\n", ret, sts);
+
+	ret = CDN_API_General_Test_Echo_Ext_blocking(state, echo_msg, echo_resp,
+		 sizeof(echo_msg), CDN_BUS_TYPE_APB);
+	 printk("CDN_API_General_Test_Echo_Ext_blocking - APB(ret = %d echo_resp = %s)\n",
+		 ret, echo_resp);
+}
+
+void hdmi_phy_init(state_struct *state, int vic, int format, int color_depth)
+{
+	int ret;
+
+	/* Configure PHY */
+	character_freq_khz = phy_cfg_hdp_ss28fdsoi(state, 4, vic, color_depth, format);
+
+	hdp_phy_reset(1);
+
+	hdmi_tx_kiran_power_configuration_seq(state, 4);
+
+	/* Set the lane swapping */
+	ret = CDN_API_General_Write_Register_blocking(state, ADDR_SOURCD_PHY + (LANES_CONFIG << 2),
+		F_SOURCE_PHY_LANE0_SWAP(3) | F_SOURCE_PHY_LANE1_SWAP(0) |
+		F_SOURCE_PHY_LANE2_SWAP(1) | F_SOURCE_PHY_LANE3_SWAP(2) |
+		F_SOURCE_PHY_COMB_BYPASS(0) | F_SOURCE_PHY_20_10(1));
+	printk("CDN_API_General_Write_Register_blocking LANES_CONFIG ret = %d\n", ret);
+}
+
+void hdmi_mode_set(state_struct *state, int vic, int format, int color_depth, int temp)
+{
+	int ret;
+	GENERAL_Read_Register_response regresp;
+
+	/* B/W Balance Type: 0 no data, 1 IT601, 2 ITU709 */
+	BT_TYPE bw_type = 0;
+	/* Mode = 0 - DVI, 1 - HDMI1.4, 2 HDMI 2.0 */
+	HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE ptype = 1;
+
+	if (vic == VIC_MODE_97_60Hz)
+		ptype = 2;
+
+	ret = CDN_API_HDMITX_Init_blocking(state);
+	printk("CDN_API_STATUS CDN_API_HDMITX_Init_blocking  ret = %d\n", ret);
+
+	/* Set HDMI TX Mode */
+	ret = CDN_API_HDMITX_Set_Mode_blocking(state, ptype, character_freq_khz);
+	printk("CDN_API_HDMITX_Set_Mode_blocking ret = %d\n", ret);
+
+	ret = CDN_API_Set_AVI(state, vic, format, bw_type);
+	printk("CDN_API_Set_AVI  ret = %d\n", ret);
+
+	ret =  CDN_API_HDMITX_SetVic_blocking(state, vic, color_depth, format);
+	printk("CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret);
+
+	/* adjust the vsync/hsync polarity */
+	CDN_API_General_Read_Register_blocking(
+					state, ADDR_SOURCE_VIF + (HSYNC2VSYNC_POL_CTRL << 2), &regresp);
+	printk("Initial HSYNC2VSYNC_POL_CTRL: 0x%x\n", regresp.val);
+	if ((regresp.val & 0x6) != 0) {
+		__raw_writel(0x4, state->mem.ss_base);
+	}
+	msleep(50);
+}
+
+int hdmi_get_edid_block(void *data, u8 *buf, u32 block, size_t len)
+{
+	HDMITX_TRANS_DATA edidResp;
+	state_struct *state = data;
+	CDN_API_STATUS ret = 0;
+
+	memset(&edidResp, 0, sizeof(edidResp));
+	switch (block) {
+	case 0:
+		ret = CDN_API_HDMITX_READ_EDID_blocking(state, 0, 0, &edidResp);
+		break;
+	case 1:
+		ret = CDN_API_HDMITX_READ_EDID_blocking(state, 0, 1, &edidResp);
+		break;
+	case 2:
+		ret = CDN_API_HDMITX_READ_EDID_blocking(state, 1, 0, &edidResp);
+		break;
+	case 3:
+		ret = CDN_API_HDMITX_READ_EDID_blocking(state, 1, 1, &edidResp);
+		break;
+	default:
+		printk("EDID block %x read not support\n", block);
+	}
+
+	memcpy(buf, edidResp.buff, 128);
+
+	return ret;
+}
+
+void hdmi_get_hpd_state(state_struct *state, u8 *hpd)
+{
+	CDN_API_HDMITX_GetHpdStatus_blocking(state, hpd);
+}

drivers/gpu/drm/imx/hdp/imx-hdmi.h

+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _IMX_HDMI_H_
+#define _IMX_HDMI_H_
+void hdmi_fw_load(state_struct *state);
+void hdmi_fw_init(state_struct *state, u32 rate);
+void hdmi_phy_init(state_struct *state, int vic, int format, int color_depth);
+void hdmi_mode_set(state_struct *state, int vic, int format, int color_depth, int max_link);
+int hdmi_get_edid_block(void *data, u8 *buf, u32 block, size_t len);
+void hdmi_get_hpd_state(state_struct *state, u8 *hpd);
+
+#endif

drivers/gpu/drm/imx/hdp/imx-hdp.h

+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _IMX_HDP_H_
+#define _IMX_HDP_H_
+
+#include <linux/regmap.h>
+#include <linux/mutex.h>
+#include <drm/drm_of.h>
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_encoder_slave.h>
+#include <soc/imx8/sc/sci.h>
+
+#include <drm/drm_dp_helper.h>
+#include "../../../../mxc/hdp/all.h"
+
+#define PLL_1188MHZ (1188000000)
+#define PLL_675MHZ (675000000)
+
+#define HDP_TX_SS_LIS_BASE   0x0000
+#define HDP_TX_SS_CSR_BASE   0x1000
+#define HDP_TX_SS_GPIO_BASE  0x2000
+#define HDP_TX_SS_CTRL0_BASE 0x8000
+
+#define CSR_PIXEL_LINK_MUX_CTL		0x00
+#define PL_MUX_CTL_VCP_OFFSET		5
+#define PL_MUX_CTL_HCP_OFFSET		4
+#define PL_MUX_CTL_PL_MUX_OFFSET	2
+#define PL_MUX_CTL_PL_SEL_OFFSET	0
+
+#define CSR_PIXEL_LINK_MUX_STATUS	0x04
+#define PL_MUX_STATUS_PL1_INT_OFFSET 18
+#define PL_MUX_STATUS_PL1_ADD_OFFSET 16
+#define PL_MUX_STATUS_PL1_TYP_OFFSET 11
+#define PL_MUX_STATUS_PL0_INT_OFFSET 9
+#define PL_MUX_STATUS_PL0_ADD_OFFSET 7
+#define PL_MUX_STATUS_PL0_TYP_OFFSET 2
+#define PL_MUX_STATUS_PL_DLY_OFFSET 0
+
+#define CSR_HDP_TX_CTRL_CTRL0		0x08
+#define CSR_HDP_TX_CTRL_CTRL1		0x0c
+
+/**
+ * imx_hdp_call - Calls a struct imx hdp_operations operation on
+ *	an entity
+ *
+ * @entity: entity where the @operation will be called
+ * @operation: type of the operation. Should be the name of a member of
+ *	struct &media_entity_operations.
+ *
+ * This helper function will check if @operation is not %NULL. On such case,
+ * it will issue a call to @operation\(@args\).
+ */
+
+#define imx_hdp_call(hdp, operation, args...)			\
+	(!(hdp) ? -ENODEV : (((hdp)->ops && (hdp)->ops->operation) ?	\
+	 (hdp)->ops->operation(args) : -ENOIOCTLCMD))
+
+struct hdp_ops {
+	void (*fw_load)(state_struct *state);
+	void (*fw_init)(state_struct *state, u32 rate);
+	void (*phy_init)(state_struct *state, int vic, int format, int color_depth);
+	void (*mode_set)(state_struct *state, int vic, int format, int color_depth, int max_link);
+	int (*get_edid_block)(void *data, u8 *buf, u32 block, size_t len);
+	void (*get_hpd_state)(state_struct *state, u8 *hpd);
+};
+
+struct hdp_devtype {
+	u8 load_fw;
+	u8 is_hdmi;
+	struct hdp_ops *ops;
+	struct hdp_rw_func *rw;
+};
+
+struct hdp_video {
+	u32 bpp;
+	u32 format;
+	u32 lanes;
+	u32 color_type; /* bt */
+	u32 color_depth;  /* bpc */
+	struct drm_display_mode cur_mode;
+	struct drm_display_mode pre_mode;
+	void __iomem *regs_base;
+};
+
+struct hdp_audio {
+	u32 interface;  /* I2S SPDIF  */
+	u32 freq;
+	u32 nlanes;
+	u32 nChannels;
+	u32 sample_width;
+	u32 sample_rate;
+	u32 audio_cts;
+	u32 audio_n;
+	bool audio_enable;
+	spinlock_t audio_lock;
+	struct mutex audio_mutex;
+	void __iomem *regs_base;
+};
+
+struct hdp_hdcp {
+	void __iomem *regs_base;
+};
+
+struct hdp_phy {
+	u32 index;
+	u32 number;
+	bool enabled;
+	struct phy *phy;
+	void __iomem *regs_base;
+};
+
+struct hdp_clks {
+	struct clk *av_pll;
+	struct clk *dig_pll;
+	struct clk *clk_ipg;
+	struct clk *clk_core;
+	struct clk *clk_pxl;
+	struct clk *clk_pxl_mux;
+	struct clk *clk_pxl_link;
+
+	struct clk *clk_hdp;
+	struct clk *clk_phy;
+	struct clk *clk_apb;
+
+	struct clk *clk_lis;
+	struct clk *clk_msi;
+	struct clk *clk_lpcg;
+	struct clk *clk_even;
+	struct clk *clk_dbl;
+	struct clk *clk_vif;
+	struct clk *clk_apb_csr;
+	struct clk *clk_apb_ctrl;
+	struct clk *av_pll_div;
+	struct clk *dig_pll_div;
+};
+
+struct imx_hdp {
+	struct device *dev;
+	struct drm_connector connector;
+	struct drm_encoder encoder;
+	struct drm_bridge bridge;
+
+	struct edid *edid;
+	char cable_state;
+	char fw_running;
+
+	void __iomem *regs_base; /* Controller regs base */
+	void __iomem *ss_base; /* HDP Subsystem regs base */
+
+	u8 load_fw;
+	u8 is_hdmi;
+
+	struct mutex mutex;		/* for state below and previous_mode */
+	enum drm_connector_force force;	/* mutex-protected force state */
+
+	struct hdp_video video;
+
+	struct drm_dp_aux aux;
+	struct mutex aux_mutex;
+
+	struct drm_dp_link dp_link;
+	S_LINK_STAT lkstat;
+	ENUM_AFE_LINK_RATE link_rate;
+
+	sc_ipc_t ipcHndl;
+	u32 mu_id;
+	u32 dual_mode;
+	struct hdp_ops *ops;
+	struct hdp_rw_func *rw;
+	struct hdp_clks clks;
+	state_struct state;
+
+};
+
+int imx_hdpaux_init(struct device *dev,	struct imx_hdp *dp);
+void imx_hdpaux_destroy(struct device *dev, struct imx_hdp *dp);
+void hdp_phy_reset(u8 reset);
+
+#endif

drivers/gpu/drm/imx/hdp/mhdp_firmware.h

+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated from dram0.data and iram0.data firmware images
+ * Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * mhdp_firmware.c
+ *
+ ******************************************************************************
+ */
+#include <linux/io.h>
+
+static u32 const mhdp_iram0[] = {
+	0x00000000,
+};
+
+static u32 const mhdp_dram0[] = {
+	0x00000000,
+};
+
+u32 const *mhdp_iram0_get_ptr(void)
+{
+    return (u32 const *)mhdp_iram0;
+}
+
+u32 const *mhdp_dram0_get_ptr(void)
+{
+    return (u32 const *)mhdp_dram0;
+}
+
+size_t mhdp_iram0_get_size(void)
+{
+    return sizeof(mhdp_iram0);
+}
+
+size_t mhdp_dram0_get_size(void)
+{
+    return sizeof(mhdp_dram0);
+}

drivers/gpu/drm/imx/hdp/ss28fdsoi_hdmitx_table.c

+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * ss28fdsoi_hdmitx_table.c
+ *
+ ******************************************************************************
+ */
+
+#include "ss28fdsoi_hdmitx_table.h"
+
+const u32 ss28fdsoi_hdmitx_clock_control_table[SS28FDSOI_HDMITX_CLOCK_CONTROL_TABLE_ROWS][SS28FDSOI_HDMITX_CLOCK_CONTROL_TABLE_COLS] = {
+    {   25000,  42500, 1000,  250000,  425000, 0x05, 0x01, 0x01, 400, 0x182, 0x00A, 2000000, 3400000, 0, 2, 2, 2, 4,  125000,  212500, 0x03,  25000,  42500 },
+    {   42500,  85000, 1000,  425000,  850000, 0x08, 0x03, 0x01, 320, 0x132, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 4,  212500,  425000, 0x02,  42500,  85000 },
+    {   85000, 170000, 1000,  850000, 1700000, 0x11, 0x00, 0x07, 340, 0x146, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 2,  425000,  850000, 0x01,  85000, 170000 },
+    {  170000, 340000, 1000, 1700000, 3400000, 0x22, 0x01, 0x07, 340, 0x146, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 1,  850000, 1700000, 0x00, 170000, 340000 },
+    {  340000, 600000, 1000, 3400000, 6000000, 0x3C, 0x03, 0x06, 600, 0x24A, 0x00A, 3400000, 6000000, 1, 1, 1, 2, 1, 1700000, 3000000, 0x00, 340000, 600000 },
+    {   25000,  34000, 1205,  312500,  425000, 0x04, 0x01, 0x01, 400, 0x182, 0x00A, 2500000, 3400000, 0, 2, 2, 2, 4,  156250,  212500, 0x03,  31250,  42500 },
+    {   34000,  68000, 1205,  425000,  850000, 0x06, 0x02, 0x01, 300, 0x11E, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 4,  212500,  425000, 0x02,  42500,  85000 },
+    {   68000, 136000, 1205,  850000, 1700000, 0x0D, 0x02, 0x02, 325, 0x137, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 2,  425000,  850000, 0x01,  85000, 170000 },
+    {  136000, 272000, 1205, 1700000, 3400000, 0x1A, 0x02, 0x04, 325, 0x137, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 1,  850000, 1700000, 0x00, 170000, 340000 },
+    {  272000, 480000, 1205, 3400000, 6000000, 0x30, 0x03, 0x05, 600, 0x24A, 0x00A, 3400000, 6000000, 1, 1, 1, 2, 1, 1700000, 3000000, 0x00, 340000, 600000 },
+    {   25000,  28000, 1500,  375000,  420000, 0x03, 0x01, 0x01, 360, 0x15A, 0x00A, 3000000, 3360000, 0, 2, 2, 2, 4,  187500,  210000, 0x03,  37500,  42000 },
+    {   28000,  56000, 1500,  420000,  840000, 0x06, 0x02, 0x01, 360, 0x15A, 0x00A, 1680000, 3360000, 0, 1, 1, 2, 4,  210000,  420000, 0x02,  42000,  84000 },
+    {   56000, 113000, 1500,  840000, 1695000, 0x0B, 0x00, 0x05, 330, 0x13C, 0x00A, 1680000, 3390000, 0, 1, 1, 2, 2,  420000,  847500, 0x01,  84000, 169500 },
+    {  113000, 226000, 1500, 1695000, 3390000, 0x16, 0x01, 0x05, 330, 0x13C, 0x00A, 1695000, 3390000, 0, 1, 1, 2, 1,  847500, 1695000, 0x00, 169500, 339000 },
+    {  226000, 400000, 1500, 3390000, 6000000, 0x28, 0x03, 0x04, 600, 0x24A, 0x00A, 3390000, 6000000, 1, 1, 1, 2, 1, 1695000, 3000000, 0x00, 339000, 600000 },
+    {   25000,  42500, 2000,  500000,  850000, 0x05, 0x01, 0x01, 400, 0x182, 0x00A, 2000000, 3400000, 0, 1, 1, 2, 4,  250000,  425000, 0x02,  50000,  85000 },
+    {   42500,  85000, 2000,  850000, 1700000, 0x08, 0x03, 0x01, 320, 0x132, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 2,  425000,  850000, 0x01,  85000, 170000 },
+    {   85000, 170000, 2000, 1700000, 3400000, 0x11, 0x00, 0x07, 340, 0x146, 0x00A, 1700000, 3400000, 0, 1, 1, 2, 1,  850000, 1700000, 0x00, 170000, 340000 },
+    {  170000, 300000, 2000, 3400000, 6000000, 0x22, 0x01, 0x06, 680, 0x29A, 0x00A, 3400000, 6000000, 1, 1, 1, 2, 1, 1700000, 3000000, 0x00, 340000, 600000 }
+};
+
+const u32 ss28fdsoi_hdmitx_pll_tuning_table[SS28FDSOI_HDMITX_PLL_TUNING_TABLE_ROWS][SS28FDSOI_HDMITX_PLL_TUNING_TABLE_COLS] = {
+	{0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 300.0, 0x08D},
+	{0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 320.0, 0x08E},
+	{0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 325.0, 0x08E},
+	{0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 330.0, 0x08E},
+	{0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 340.0, 0x08F},
+	{0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 360.0, 0x0A7},
+	{0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 400.0, 0x0C5},
+	{1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 300.0, 0x086},
+	{1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 320.0, 0x087},
+	{1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 325.0, 0x087},
+	{1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 330.0, 0x104},
+	{1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 340.0, 0x08B},
+	{1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 360.0, 0x08D},
+	{1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 400.0, 0x0A6},
+	{2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 300.0, 0x04E},
+	{2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 320.0, 0x04F},
+	{2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 325.0, 0x04F},
+	{2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 330.0, 0x085},
+	{2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 340.0, 0x085},
+	{2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 360.0, 0x086},
+	{2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 400.0, 0x08B},
+	{3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 300.0, 0x047},
+	{3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 320.0, 0x04B},
+	{3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 325.0, 0x04B},
+	{3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 330.0, 0x04B},
+	{3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 340.0, 0x04D},
+	{3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 360.0, 0x04E},
+	{3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 400.0, 0x085},
+	{4, 3400000, 3900000, 0x7, 0x1, 0x0, 0x8E, 0x2F, 600.0, 0x08D},
+	{4, 3400000, 3900000, 0x7, 0x1, 0x0, 0x8E, 0x2F, 680.0, 0x0A6},
+	{5, 3900000, 4500000, 0x7, 0x1, 0x0, 0x8E, 0x2F, 600.0, 0x087},
+	{5, 3900000, 4500000, 0x7, 0x1, 0x0, 0x8E, 0x2F, 680.0, 0x0A4},
+	{6, 4500000, 5200000, 0x7, 0x1, 0x0, 0x04, 0x0D, 600.0, 0x04F},
+	{6, 4500000, 5200000, 0x7, 0x1, 0x0, 0x04, 0x0D, 680.0, 0x086},
+	{7, 5200000, 6000000, 0x7, 0x1, 0x0, 0x04, 0x0D, 600.0, 0x04D},
+	{7, 5200000, 6000000, 0x7, 0x1, 0x0, 0x04, 0x0D, 680.0, 0x04F}
+};

drivers/gpu/drm/imx/hdp/ss28fdsoi_hdmitx_table.h

+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * ss28fdsoi_hdmitx_table.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef SS28FDSOI_HDMITX_TABLE_H_
+#define SS28FDSOI_HDMITX_TABLE_H_
+
+#include <linux/io.h>
+
+# define SS28FDSOI_HDMITX_CLOCK_CONTROL_TABLE_ROWS 19
+# define SS28FDSOI_HDMITX_CLOCK_CONTROL_TABLE_COLS 23
+
+# define SS28FDSOI_HDMITX_PLL_TUNING_TABLE_ROWS 36
+# define SS28FDSOI_HDMITX_PLL_TUNING_TABLE_COLS 19
+
+typedef enum {
+	//PIXEL_CLK_FREQ_MHZ_MIN,
+	PIXEL_CLK_FREQ_KHZ_MIN,
+	//PIXEL_CLK_FREQ_MHZ_MAX,
+	PIXEL_CLK_FREQ_KHZ_MAX,
+	FEEDBACK_FACTOR,
+	DATA_RANGE_MBPS_MIN,
+	DATA_RANGE_MBPS_MAX,
+	CMNDA_PLL0_IP_DIV,
+	CMN_REF_CLK_DIG_DIV,
+	REF_CLK_DIVIDER_SCALER,
+	PLL_FB_DIV_TOTAL,
+	CMNDA_PLL0_FB_DIV_LOW,
+	CMNDA_PLL0_FB_DIV_HIGH,
+	//VCO_FREQ_MHZ_MIN,
+	//VCO_FREQ_MHZ_MAX,
+	VCO_FREQ_KHZ_MIN,
+	VCO_FREQ_KHZ_MAX,
+	VCO_RING_SELECT,
+	CMNDA_HS_CLK_0_SEL,
+	CMNDA_HS_CLK_1_SEL,
+	HSCLK_DIV_AT_XCVR,
+	HSCLK_DIV_TX_SUB_RATE,
+	TX_CLK_KHZ_MIN,
+	TX_CLK_KHZ_MAX,
+	CMNDA_PLL0_HS_SYM_DIV_SEL,
+	CMNDA_PLL0_CLK_FREQ_KHZ_MIN,
+	CMNDA_PLL0_CLK_FREQ_KHZ_MAX
+} CLK_CTRL_PARAM;
+
+typedef enum {
+	VCO_FREQ_BIN,
+	/* PLL_VCO_FREQ_MHZ_MIN, */
+	/* PLL_VCO_FREQ_MHZ_MAX, */
+	PLL_VCO_FREQ_KHZ_MIN,
+	PLL_VCO_FREQ_KHZ_MAX,
+	VOLTAGE_TO_CURRENT_COARSE,
+	VOLTAGE_TO_CURRENT,
+	NDAC_CTRL,
+	PMOS_CTRL,
+	PTAT_NDAC_CTRL,
+	/*PLL_FEEDBACK_DIV_TOTAL,  float to int */
+	PLL_FEEDBACK_DIV_TOTAL,
+	CHARGE_PUMP_GAIN
+} PLL_TUNE_PARAM;
+
+extern const u32
+ss28fdsoi_hdmitx_clock_control_table[SS28FDSOI_HDMITX_CLOCK_CONTROL_TABLE_ROWS]
+    [SS28FDSOI_HDMITX_CLOCK_CONTROL_TABLE_COLS];
+extern const u32
+ss28fdsoi_hdmitx_pll_tuning_table[SS28FDSOI_HDMITX_PLL_TUNING_TABLE_ROWS]
+    [SS28FDSOI_HDMITX_PLL_TUNING_TABLE_COLS];
+
+#endif