[C43] fix uart support

CN49: RS232 (UART2), RS232 TTL (UART3)
CN50: RS485 (UART4)

arch/arm64/boot/dts/seco/seco-imx8qm-c43.dts

@@ -418,7 +418,7 @@
  * |                                    UART                                  |
  * |__________________________________________________________________________|
  */
-&lpuart0 {
+&lpuart0 { /* console */
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpuart0>;
 	status = "okay";
@@ -432,21 +432,27 @@
 	status = "okay";
 };
 
-&lpuart2 { /* Dbg console */
+&lpuart2 { /* RS232 */
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpuart2>;
-	status = "disabled";
+	status = "okay";
 };
 
-&lpuart3 { /* MKbus */
+&lpuart3 { /* RS232 TTL */
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpuart3>;
-	status = "disabled";
+	rts-gpios = <&lsio_gpio1 14 GPIO_ACTIVE_HIGH>;
+	cts-gpios = <&lsio_gpio1 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
 };
 
-&lpuart4 { /* uart 4 */
+&lpuart4 { /* RS485 */
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpuart4>;
+	linux,rs485-enabled-at-boot-time;
+	rs485-rx-during-tx;
+	uart-has-rtscts;
+	rts-gpios = <&lsio_gpio0 19 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 /*  __________________________________________________________________________
@@ -1004,12 +1010,6 @@ ldb1_backlight: lvds_backlight@0 {
 	status = "disabled";
 
 };
-
-&pwm_lvds1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm_lvds1>;
-	status = "okay";
-};
 /*  __________________________________________________________________________
  * |__________________________________________________________________________|
  */
@@ -1111,7 +1111,8 @@ ldb1_backlight: lvds_backlight@0 {
 			IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07	0x00000021
 			/* SATA PCIE */
 			IMX8QM_MLB_CLK_LSIO_GPIO3_IO27		0x00000021
-			/* ENPW R_UART1 */
+			/* ENPWR_UART1 */
+			IMX8QM_LVDS1_GPIO00_LSIO_GPIO1_IO10 	0x00000021
 			/* Generic Gpios */
 			IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21	0x00000021 /* Q7_GPIO0 */
 			IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20	0x00000021 /* Q7_GPIO2 */
@@ -1241,8 +1242,8 @@ ldb1_backlight: lvds_backlight@0 {
 		fsl,pins = <
 			IMX8QM_M41_GPIO0_00_DMA_UART3_RX	0x06000020
 			IMX8QM_M41_GPIO0_01_DMA_UART3_TX	0x06000020
-			IMX8QM_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14	0x00000021
-			IMX8QM_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15	0x00000021
+			IMX8QM_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14	0x00000021 /* UART3_RTS_SW */
+			IMX8QM_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15	0x00000021 /* UART3_CTS_SW */
 		>;
 	};
 
@@ -1250,6 +1251,8 @@ ldb1_backlight: lvds_backlight@0 {
 		fsl,pins = <
 			IMX8QM_M40_GPIO0_00_DMA_UART4_RX	0x06000020
 			IMX8QM_M40_GPIO0_01_DMA_UART4_TX	0x06000020
+			IMX8QM_GPT1_COMPARE_LSIO_GPIO0_IO19	0x00000021 /* UART4_DE_SW */
+			IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30	0x00000021 /* UART4_RE#_SW - DNP */
 		>;
 	};
 
@@ -1569,12 +1572,6 @@ ldb1_backlight: lvds_backlight@0 {
 	    >;
     };
 
-	pinctrl_pwm_lvds1: pwmlvds1grp {
-		fsl,pins = <
-			IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT		0x00000020
-		>;
-	};
-
 	pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 {
 		fsl,pins = <
 			IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL	0xc2000020