When running the below system suspend/resume test case on
i.MX8ulp EVK platform with the RM68200 MIPI DSI panel enabled,
DCNANO display controller power usage count and pixel clock enable
count would be unbalanced when the DRM connector's DPMS property
is changed from off to on after system resumes, if the DPMS property
is off before system suspends.  The root cause is that the
crtc_helper_funcs->mode_set_nofb() is called twice during the
procedure without crtc disablement, one at system resume stage and
one for DPMS on operation.  That means the pm_runtime_get_sync()
would be called twice at that function and pixel clock would be
enabled twice as well.  This patch introduces a flag to indicate
if the modeset is done or not to avoid the doulbe modeset so that
the reference counts are balanced.

while true; do modetest -M imx-dcnano -w 34:DPMS:3; done &
while true; do /unit_tests/SRTC/rtcwakeup.out -s 2 -m mem; done

Fixes: ce68244e ("MLK-25531-2 drm/imx: Add dcnano drm support")
Cc: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>