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/*
* PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
*
* Copyright (c) 2008-2009 USI Co., Ltd.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
*/
#include <linux/slab.h>
#include "pm8001_sas.h"
#include "pm8001_hwi.h"
#include "pm8001_chips.h"
#include "pm8001_ctl.h"
/**
* read_main_config_table - read the configure table and save it.
* @pm8001_ha: our hba card information
*/
static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
{
void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
pm8001_ha->main_cfg_tbl.pm8001_tbl.signature =
pm8001_mr32(address, 0x00);
pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
pm8001_mr32(address, 0x04);
pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
pm8001_mr32(address, 0x08);
pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io =
pm8001_mr32(address, 0x0C);
pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl =
pm8001_mr32(address, 0x10);
pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
pm8001_mr32(address, 0x14);
pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset =
pm8001_mr32(address, 0x18);
pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
pm8001_mr32(address, MAIN_IBQ_OFFSET);
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
pm8001_mr32(address, MAIN_OBQ_OFFSET);
pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag =
pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
/* read analog Setting offset from the configuration table */
pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
/* read Error Dump Offset and Length */
pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
}
/**
* read_general_status_table - read the general status table and save it.
* @pm8001_ha: our hba card information
*/
static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
{
void __iomem *address = pm8001_ha->general_stat_tbl_addr;
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pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate =
pm8001_mr32(address, 0x00);
pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 =
pm8001_mr32(address, 0x04);
pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 =
pm8001_mr32(address, 0x08);
pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt =
pm8001_mr32(address, 0x0C);
pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt =
pm8001_mr32(address, 0x10);
pm8001_ha->gs_tbl.pm8001_tbl.rsvd =
pm8001_mr32(address, 0x14);
pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] =
pm8001_mr32(address, 0x18);
pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] =
pm8001_mr32(address, 0x1C);
pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] =
pm8001_mr32(address, 0x20);
pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] =
pm8001_mr32(address, 0x24);
pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] =
pm8001_mr32(address, 0x28);
pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] =
pm8001_mr32(address, 0x2C);
pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] =
pm8001_mr32(address, 0x30);
pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] =
pm8001_mr32(address, 0x34);
pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val =
pm8001_mr32(address, 0x38);
pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] =
pm8001_mr32(address, 0x3C);
pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] =
pm8001_mr32(address, 0x40);
pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] =
pm8001_mr32(address, 0x44);
pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] =
pm8001_mr32(address, 0x48);
pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] =
pm8001_mr32(address, 0x4C);
pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] =
pm8001_mr32(address, 0x50);
pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] =
pm8001_mr32(address, 0x54);
pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] =
pm8001_mr32(address, 0x58);
pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] =
pm8001_mr32(address, 0x5C);
pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] =
pm8001_mr32(address, 0x60);
}
/**
* read_inbnd_queue_table - read the inbound queue table and save it.
* @pm8001_ha: our hba card information
*/
static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
{
int i;
void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
u32 offset = i * 0x20;
pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
pm8001_ha->inbnd_q_tbl[i].pi_offset =
pm8001_mr32(address, (offset + 0x18));
}
}
/**
* read_outbnd_queue_table - read the outbound queue table and save it.
* @pm8001_ha: our hba card information
*/
static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
{
int i;
void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
u32 offset = i * 0x24;
pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
pm8001_ha->outbnd_q_tbl[i].ci_offset =
pm8001_mr32(address, (offset + 0x18));
}
}
/**
* init_default_table_values - init the default table.
* @pm8001_ha: our hba card information
*/
static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
{
int i;
u32 offsetib, offsetob;
void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0;
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0;
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0;
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0;
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0;
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
0;
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
0;
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr =
pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr =
pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size =
PM8001_EVENT_LOG_SIZE;
pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01;
pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr =
pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr =
pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size =
PM8001_EVENT_LOG_SIZE;
pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01;
pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01;
for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
PM8001_MPI_QUEUE | (64 << 16) | (0x00<<30);
pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
pm8001_ha->inbnd_q_tbl[i].base_virt =
(u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
pm8001_ha->inbnd_q_tbl[i].total_length =
pm8001_ha->memoryMap.region[IB + i].total_len;
pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
pm8001_ha->memoryMap.region[CI + i].virt_ptr;
offsetib = i * 0x20;
pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
get_pci_bar_index(pm8001_mr32(addressib,
(offsetib + 0x14)));
pm8001_ha->inbnd_q_tbl[i].pi_offset =
pm8001_mr32(addressib, (offsetib + 0x18));
pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
}
for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
PM8001_MPI_QUEUE | (64 << 16) | (0x01<<30);
pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
pm8001_ha->outbnd_q_tbl[i].base_virt =
(u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
pm8001_ha->outbnd_q_tbl[i].total_length =
pm8001_ha->memoryMap.region[OB + i].total_len;
pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
0 | (10 << 16) | (i << 24);
pm8001_ha->memoryMap.region[PI + i].virt_ptr;
offsetob = i * 0x24;
pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
get_pci_bar_index(pm8001_mr32(addressob,
offsetob + 0x14));
pm8001_ha->outbnd_q_tbl[i].ci_offset =
pm8001_mr32(addressob, (offsetob + 0x18));
pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
}
}
/**
* update_main_config_table - update the main default table to the HBA.
* @pm8001_ha: our hba card information
*/
static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
{
void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
pm8001_mw32(address, 0x24,
pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
pm8001_ha->main_cfg_tbl.pm8001_tbl.
outbound_tgt_ITNexus_event_pid0_3);
pm8001_ha->main_cfg_tbl.pm8001_tbl.
outbound_tgt_ITNexus_event_pid4_7);
pm8001_ha->main_cfg_tbl.pm8001_tbl.
outbound_tgt_ssp_event_pid0_3);
pm8001_ha->main_cfg_tbl.pm8001_tbl.
outbound_tgt_ssp_event_pid4_7);
pm8001_ha->main_cfg_tbl.pm8001_tbl.
outbound_tgt_smp_event_pid0_3);
pm8001_ha->main_cfg_tbl.pm8001_tbl.
outbound_tgt_smp_event_pid4_7);
pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
pm8001_mw32(address, 0x58,
pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
pm8001_mw32(address, 0x5C,
pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
pm8001_mw32(address, 0x68,
pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
}
/**
* update_inbnd_queue_table - update the inbound queue table to the HBA.
* @pm8001_ha: our hba card information
*/
static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
int number)
{
void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
u16 offset = number * 0x20;
pm8001_mw32(address, offset + 0x00,
pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
pm8001_mw32(address, offset + 0x04,
pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
pm8001_mw32(address, offset + 0x08,
pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
pm8001_mw32(address, offset + 0x0C,
pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
pm8001_mw32(address, offset + 0x10,
pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
}
/**
* update_outbnd_queue_table - update the outbound queue table to the HBA.
* @pm8001_ha: our hba card information
*/
static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
int number)
{
void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
u16 offset = number * 0x24;
pm8001_mw32(address, offset + 0x00,
pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
pm8001_mw32(address, offset + 0x04,
pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
pm8001_mw32(address, offset + 0x08,
pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
pm8001_mw32(address, offset + 0x0C,
pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
pm8001_mw32(address, offset + 0x10,
pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
pm8001_mw32(address, offset + 0x1C,
pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
}
/**
* pm8001_bar4_shift - function is called to shift BAR base address
* @pm8001_ha : our hba card infomation
* @shiftValue : shifting value in memory bar.
*/
int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
/* program the inbound AXI translation Lower Address */
pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
/* confirm the setting is written */
do {
regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
} while ((regVal != shiftValue) && time_before(jiffies, start));
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
" = 0x%x\n", regVal));
return -1;
}
return 0;
}
/**
* mpi_set_phys_g3_with_ssc
* @pm8001_ha: our hba card information
* @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
*/
static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
u32 SSCbit)
jack wang
committed
u32 value, offset, i;
#define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
#define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
#define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
#define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
#define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
#define PHY_G3_WITH_SSC_BIT_SHIFT 13
#define SNW3_PHY_CAPABILITIES_PARITY 31
/*
* Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
* Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
*/
spin_lock_irqsave(&pm8001_ha->lock, flags);
if (-1 == pm8001_bar4_shift(pm8001_ha,
SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
jack wang
committed
for (i = 0; i < 4; i++) {
offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
jack wang
committed
pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
}
/* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
if (-1 == pm8001_bar4_shift(pm8001_ha,
SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
for (i = 4; i < 8; i++) {
offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
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committed
pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
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/*************************************************************
Change the SSC upspreading value to 0x0 so that upspreading is disabled.
Device MABC SMOD0 Controls
Address: (via MEMBASE-III):
Using shifted destination address 0x0_0000: with Offset 0xD8
31:28 R/W Reserved Do not change
27:24 R/W SAS_SMOD_SPRDUP 0000
23:20 R/W SAS_SMOD_SPRDDN 0000
19:0 R/W Reserved Do not change
Upon power-up this register will read as 0x8990c016,
and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
so that the written value will be 0x8090c016.
This will ensure only down-spreading SSC is enabled on the SPC.
*************************************************************/
value = pm8001_cr32(pm8001_ha, 2, 0xd8);
pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
/*set the shifted destination address to 0x0 to avoid error operation */
pm8001_bar4_shift(pm8001_ha, 0x0);
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
return;
}
/**
* mpi_set_open_retry_interval_reg
* @pm8001_ha: our hba card information
* @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
*/
static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
u32 interval)
{
u32 offset;
u32 value;
u32 i;
#define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
#define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
#define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
#define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
#define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
spin_lock_irqsave(&pm8001_ha->lock, flags);
/* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
if (-1 == pm8001_bar4_shift(pm8001_ha,
OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
for (i = 0; i < 4; i++) {
offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
pm8001_cw32(pm8001_ha, 2, offset, value);
}
if (-1 == pm8001_bar4_shift(pm8001_ha,
OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
for (i = 4; i < 8; i++) {
offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
pm8001_cw32(pm8001_ha, 2, offset, value);
}
/*set the shifted destination address to 0x0 to avoid error operation */
pm8001_bar4_shift(pm8001_ha, 0x0);
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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return;
}
/**
* mpi_init_check - check firmware initialization status.
* @pm8001_ha: our hba card information
*/
static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
{
u32 max_wait_count;
u32 value;
u32 gst_len_mpistate;
/* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
table is updated */
pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
/* wait until Inbound DoorBell Clear Register toggled */
max_wait_count = 1 * 1000 * 1000;/* 1 sec */
do {
udelay(1);
value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
value &= SPC_MSGU_CFG_TABLE_UPDATE;
} while ((value != 0) && (--max_wait_count));
if (!max_wait_count)
return -1;
/* check the MPI-State for initialization */
gst_len_mpistate =
pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
GST_GSTLEN_MPIS_OFFSET);
if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
return -1;
/* check MPI Initialization error */
gst_len_mpistate = gst_len_mpistate >> 16;
if (0x0000 != gst_len_mpistate)
return -1;
return 0;
}
/**
* check_fw_ready - The LLDD check if the FW is ready, if not, return error.
* @pm8001_ha: our hba card information
*/
static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
{
u32 value, value1;
u32 max_wait_count;
/* check error state */
value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
/* check AAP error */
if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
/* error state */
value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
return -1;
}
/* check IOP error */
if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
/* error state */
value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
return -1;
}
/* bit 4-31 of scratch pad1 should be zeros if it is not
in error state*/
if (value & SCRATCH_PAD1_STATE_MASK) {
/* error case */
pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
return -1;
}
/* bit 2, 4-31 of scratch pad2 should be zeros if it is not
in error state */
if (value1 & SCRATCH_PAD2_STATE_MASK) {
/* error case */
return -1;
}
max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
/* wait until scratch pad 1 and 2 registers in ready state */
do {
udelay(1);
value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
& SCRATCH_PAD1_RDY;
value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
& SCRATCH_PAD2_RDY;
if ((--max_wait_count) == 0)
return -1;
} while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
return 0;
}
static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
{
void __iomem *base_addr;
u32 value;
u32 offset;
u32 pcibar;
u32 pcilogic;
value = pm8001_cr32(pm8001_ha, 0, 0x44);
offset = value & 0x03FFFFFF;
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
pcilogic = (value & 0xFC000000) >> 26;
pcibar = get_pci_bar_index(pcilogic);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
pm8001_ha->main_cfg_tbl_addr = base_addr =
pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
pm8001_ha->general_stat_tbl_addr =
base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
pm8001_ha->inbnd_q_tbl_addr =
base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
pm8001_ha->outbnd_q_tbl_addr =
base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
}
/**
* pm8001_chip_init - the main init function that initialize whole PM8001 chip.
* @pm8001_ha: our hba card information
*/
static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
/* check the firmware status */
if (-1 == check_fw_ready(pm8001_ha)) {
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("Firmware is not ready!\n"));
return -EBUSY;
}
/* Initialize pci space address eg: mpi offset */
init_pci_device_addresses(pm8001_ha);
init_default_table_values(pm8001_ha);
read_main_config_table(pm8001_ha);
read_general_status_table(pm8001_ha);
read_inbnd_queue_table(pm8001_ha);
read_outbnd_queue_table(pm8001_ha);
/* update main config table ,inbound table and outbound table */
update_main_config_table(pm8001_ha);
for (i = 0; i < PM8001_MAX_INB_NUM; i++)
update_inbnd_queue_table(pm8001_ha, i);
for (i = 0; i < PM8001_MAX_OUTB_NUM; i++)
update_outbnd_queue_table(pm8001_ha, i);
mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
Mark Salyzyn
committed
/* 7->130ms, 34->500ms, 119->1.5s */
mpi_set_open_retry_interval_reg(pm8001_ha, 119);
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/* notify firmware update finished and check initialization status */
if (0 == mpi_init_check(pm8001_ha)) {
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("MPI initialize successful!\n"));
} else
return -EBUSY;
/*This register is a 16-bit timer with a resolution of 1us. This is the
timer used for interrupt delay/coalescing in the PCIe Application Layer.
Zero is not a valid value. A value of 1 in the register will cause the
interrupts to be normal. A value greater than 1 will cause coalescing
delays.*/
pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
return 0;
}
static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
{
u32 max_wait_count;
u32 value;
u32 gst_len_mpistate;
init_pci_device_addresses(pm8001_ha);
/* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
table is stop */
pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
/* wait until Inbound DoorBell Clear Register toggled */
max_wait_count = 1 * 1000 * 1000;/* 1 sec */
do {
udelay(1);
value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
value &= SPC_MSGU_CFG_TABLE_RESET;
} while ((value != 0) && (--max_wait_count));
if (!max_wait_count) {
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
return -1;
}
/* check the MPI-State for termination in progress */
/* wait until Inbound DoorBell Clear Register toggled */
max_wait_count = 1 * 1000 * 1000; /* 1 sec */
do {
udelay(1);
gst_len_mpistate =
pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
GST_GSTLEN_MPIS_OFFSET);
if (GST_MPI_STATE_UNINIT ==
(gst_len_mpistate & GST_MPI_STATE_MASK))
break;
} while (--max_wait_count);
if (!max_wait_count) {
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk(" TIME OUT MPI State = 0x%x\n",
gst_len_mpistate & GST_MPI_STATE_MASK));
return -1;
}
return 0;
}
/**
* soft_reset_ready_check - Function to check FW is ready for soft reset.
* @pm8001_ha: our hba card information
*/
static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
{
u32 regVal, regVal1, regVal2;
if (mpi_uninit_check(pm8001_ha) != 0) {
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("MPI state is not ready\n"));
return -1;
}
/* read the scratch pad 2 register bit 2 */
regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
& SCRATCH_PAD2_FWRDY_RST;
if (regVal == SCRATCH_PAD2_FWRDY_RST) {
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("Firmware is ready for reset .\n"));
} else {
unsigned long flags;
/* Trigger NMI twice via RB6 */
spin_lock_irqsave(&pm8001_ha->lock, flags);
if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("Shift Bar4 to 0x%x failed\n",
RB6_ACCESS_REG));
return -1;
}
pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
RB6_MAGIC_NUMBER_RST);
pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
/* wait for 100 ms */
mdelay(100);
regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
SCRATCH_PAD2_FWRDY_RST;
if (regVal != SCRATCH_PAD2_FWRDY_RST) {
regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
"=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
regVal1, regVal2));
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
}
return 0;
}
/**
* pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
* the FW register status to the originated status.
* @pm8001_ha: our hba card information
* @signature: signature in host scratch pad0 register.
*/
static int
pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
{
u32 regVal, toggleVal;
u32 max_wait_count;
u32 regVal1, regVal2, regVal3;
/* step1: Check FW is ready for soft reset */
if (soft_reset_ready_check(pm8001_ha) != 0) {
PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
return -1;
}
/* step 2: clear NMI status register on AAP1 and IOP, write the same
value to clear */
/* map 0x60000 to BAR4(0x20), BAR2(win) */
spin_lock_irqsave(&pm8001_ha->lock, flags);
if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("Shift Bar4 to 0x%x failed\n",
MBIC_AAP1_ADDR_BASE));
return -1;
}
regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
/* map 0x70000 to BAR4(0x20), BAR2(win) */
if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("Shift Bar4 to 0x%x failed\n",
MBIC_IOP_ADDR_BASE));
return -1;
}
regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal));
pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
/* read the scratch pad 1 register bit 2 */
regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
& SCRATCH_PAD1_RST;
toggleVal = regVal ^ SCRATCH_PAD1_RST;
/* set signature in host scratch pad0 register to tell SPC that the
host performs the soft reset */
pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
/* read required registers for confirmming */
/* map 0x0700000 to BAR4(0x20), BAR2(win) */
if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("Shift Bar4 to 0x%x failed\n",
GSM_ADDR_BASE));
return -1;
}
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
" Reset = 0x%x\n",
pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
/* step 3: host read GSM Configuration and Reset register */
regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
/* Put those bits to low */
/* GSM XCBI offset = 0x70 0000
0x00 Bit 13 COM_SLV_SW_RSTB 1
0x00 Bit 12 QSSP_SW_RSTB 1
0x00 Bit 11 RAAE_SW_RSTB 1
0x00 Bit 9 RB_1_SW_RSTB 1
0x00 Bit 8 SM_SW_RSTB 1
*/
regVal &= ~(0x00003b00);
/* host write GSM Configuration and Reset register */
pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
"Configuration and Reset is set to = 0x%x\n",
pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
/* step 4: */
/* disable GSM - Read Address Parity Check */
regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("GSM 0x700038 - Read Address Parity Check "
"Enable = 0x%x\n", regVal1));
pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
"is set to = 0x%x\n",
pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
/* disable GSM - Write Address Parity Check */
regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("GSM 0x700040 - Write Address Parity Check"
" Enable = 0x%x\n", regVal2));
pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("GSM 0x700040 - Write Address Parity Check "
"Enable is set to = 0x%x\n",
pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
/* disable GSM - Write Data Parity Check */
regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("GSM 0x300048 - Write Data Parity Check"
" Enable = 0x%x\n", regVal3));
pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
"is set to = 0x%x\n",
pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
/* step 5: delay 10 usec */
udelay(10);
/* step 5-b: set GPIO-0 output control to tristate anyway */
if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("Shift Bar4 to 0x%x failed\n",
GPIO_ADDR_BASE));
return -1;
}
regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("GPIO Output Control Register:"
" = 0x%x\n", regVal));
/* set GPIO-0 output control to tri-state */
regVal &= 0xFFFFFFFC;
pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
/* Step 6: Reset the IOP and AAP1 */
/* map 0x00000 to BAR4(0x20), BAR2(win) */
if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
SPC_TOP_LEVEL_ADDR_BASE));
return -1;
}
regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("Top Register before resetting IOP/AAP1"
":= 0x%x\n", regVal));
regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
/* step 7: Reset the BDMA/OSSP */
regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("Top Register before resetting BDMA/OSSP"
": = 0x%x\n", regVal));
regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
/* step 8: delay 10 usec */
udelay(10);
/* step 9: bring the BDMA and OSSP out of reset */
regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("Top Register before bringing up BDMA/OSSP"
":= 0x%x\n", regVal));
regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
/* step 10: delay 10 usec */
udelay(10);
/* step 11: reads and sets the GSM Configuration and Reset Register */
/* map 0x0700000 to BAR4(0x20), BAR2(win) */
if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
spin_unlock_irqrestore(&pm8001_ha->lock, flags);
PM8001_FAIL_DBG(pm8001_ha,
pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
GSM_ADDR_BASE));
return -1;
}
PM8001_INIT_DBG(pm8001_ha,
pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
"Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
/* Put those bits to high */
/* GSM XCBI offset = 0x70 0000
0x00 Bit 13 COM_SLV_SW_RSTB 1
0x00 Bit 12 QSSP_SW_RSTB 1
0x00 Bit 11 RAAE_SW_RSTB 1