Kconfig

# SPDX-License-Identifier: GPL-2.0
config ARM
	bool
	default y
	select ARCH_32BIT_OFF_T
	select ARCH_HAS_BINFMT_FLAT
	select ARCH_HAS_DEBUG_VIRTUAL if MMU
	select ARCH_HAS_DEVMEM_IS_ALLOWED
	select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
	select ARCH_HAS_ELF_RANDOMIZE
	select ARCH_HAS_FORTIFY_SOURCE
	select ARCH_HAS_KEEPINITRD
	select ARCH_HAS_KCOV
	select ARCH_HAS_MEMBARRIER_SYNC_CORE
	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
	select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
	select ARCH_HAS_PHYS_TO_DMA
	select ARCH_HAS_SETUP_DMA_OPS
	select ARCH_HAS_SET_MEMORY
	select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
	select ARCH_HAS_STRICT_MODULE_RWX if MMU
	select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
	select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
	select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
	select ARCH_HAVE_CUSTOM_GPIO_H
	select ARCH_HAS_GCOV_PROFILE_ALL
	select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC
	select ARCH_MIGHT_HAVE_PC_PARPORT
	select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
	select ARCH_SUPPORTS_ATOMIC_RMW
	select ARCH_USE_BUILTIN_BSWAP
	select ARCH_USE_CMPXCHG_LOCKREF
	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
	select ARCH_WANT_IPC_PARSE_VERSION
	select ARCH_WANT_LD_ORPHAN_WARN
	select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
	select BUILDTIME_TABLE_SORT if MMU
	select CLONE_BACKWARDS
	select CPU_PM if SUSPEND || CPU_IDLE
	select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
	select DMA_DECLARE_COHERENT
	select DMA_OPS
	select DMA_REMAP if MMU
	select EDAC_SUPPORT
	select EDAC_ATOMIC_SCRUB
	select GENERIC_ALLOCATOR
	select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
	select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
	select GENERIC_IRQ_IPI if SMP
	select GENERIC_CPU_AUTOPROBE
	select GENERIC_EARLY_IOREMAP
	select GENERIC_IDLE_POLL_SETUP
	select GENERIC_IRQ_PROBE
	select GENERIC_IRQ_SHOW
	select GENERIC_IRQ_SHOW_LEVEL
	select GENERIC_PCI_IOMAP
	select GENERIC_SCHED_CLOCK
	select GENERIC_SMP_IDLE_THREAD
	select GENERIC_STRNCPY_FROM_USER
	select GENERIC_STRNLEN_USER
	select HANDLE_DOMAIN_IRQ
	select HARDIRQS_SW_RESEND
	select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
	select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
	select HAVE_ARCH_MMAP_RND_BITS if MMU
	select HAVE_ARCH_SECCOMP
	select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
	select HAVE_ARCH_TRACEHOOK
	select HAVE_ARM_SMCCC if CPU_V7
	select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
	select HAVE_CONTEXT_TRACKING
	select HAVE_C_RECORDMCOUNT
	select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
	select HAVE_DMA_CONTIGUOUS if MMU
	select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
	select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
	select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
	select HAVE_EXIT_THREAD
	select HAVE_FAST_GUP if ARM_LPAE
	select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
	select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
	select HAVE_FUNCTION_TRACER if !XIP_KERNEL
	select HAVE_GCC_PLUGINS
	select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
	select HAVE_IDE if PCI || ISA || PCMCIA
	select HAVE_IRQ_TIME_ACCOUNTING
	select HAVE_KERNEL_GZIP
	select HAVE_KERNEL_LZ4
	select HAVE_KERNEL_LZMA
	select HAVE_KERNEL_LZO
	select HAVE_KERNEL_XZ
	select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
	select HAVE_KRETPROBES if HAVE_KPROBES
	select HAVE_MOD_ARCH_SPECIFIC
	select HAVE_NMI
	select HAVE_OPROFILE if HAVE_PERF_EVENTS
	select HAVE_OPTPROBES if !THUMB2_KERNEL
	select HAVE_PERF_EVENTS
	select HAVE_PERF_REGS
	select HAVE_PERF_USER_STACK_DUMP
	select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
	select HAVE_REGS_AND_STACK_ACCESS_API
	select HAVE_RSEQ
	select HAVE_STACKPROTECTOR
	select HAVE_SYSCALL_TRACEPOINTS
	select HAVE_UID16
	select HAVE_VIRT_CPU_ACCOUNTING_GEN
	select IRQ_FORCED_THREADING
	select MODULES_USE_ELF_REL
	select NEED_DMA_MAP_STATE
	select OF_EARLY_FLATTREE if OF
	select OLD_SIGACTION
	select OLD_SIGSUSPEND3
	select PCI_SYSCALL if PCI
	select PERF_USE_VMALLOC
	select RTC_LIB
	select SET_FS
	select SYS_SUPPORTS_APM_EMULATION
	# Above selects are sorted alphabetically; please add new ones
	# according to that.  Thanks.
	help
	  The ARM series is a line of low-power-consumption RISC chip designs
	  licensed by ARM Ltd and targeted at embedded applications and
	  handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
	  manufactured, but legacy ARM-based PC hardware remains popular in
	  Europe.  There is an ARM Linux project with a web page at
	  <http://www.arm.linux.org.uk/>.

config ARM_HAS_SG_CHAIN
	bool

config ARM_DMA_USE_IOMMU
	bool
	select ARM_HAS_SG_CHAIN
	select NEED_SG_DMA_LENGTH

if ARM_DMA_USE_IOMMU

config ARM_DMA_IOMMU_ALIGNMENT
	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
	range 4 9
	default 8
	help
	  DMA mapping framework by default aligns all buffers to the smallest
	  PAGE_SIZE order which is greater than or equal to the requested buffer
	  size. This works well for buffers up to a few hundreds kilobytes, but
	  for larger buffers it just a waste of address space. Drivers which has
	  relatively small addressing window (like 64Mib) might run out of
	  virtual space with just a few allocations.

	  With this parameter you can specify the maximum PAGE_SIZE order for
	  DMA IOMMU buffers. Larger buffers will be aligned only to this
	  specified order. The order is expressed as a power of two multiplied
	  by the PAGE_SIZE.

endif

config SYS_SUPPORTS_APM_EMULATION
	bool

config HAVE_TCM
	bool
	select GENERIC_ALLOCATOR

config HAVE_PROC_CPU
	bool

config NO_IOPORT_MAP
	bool

config SBUS
	bool

config STACKTRACE_SUPPORT
	bool
	default y

config LOCKDEP_SUPPORT
	bool
	default y

config TRACE_IRQFLAGS_SUPPORT
	bool
	default !CPU_V7M

config ARCH_HAS_ILOG2_U32
	bool

config ARCH_HAS_ILOG2_U64
	bool

config ARCH_HAS_BANDGAP
	bool

config FIX_EARLYCON_MEM
	def_bool y if MMU

config GENERIC_HWEIGHT
	bool
	default y

config GENERIC_CALIBRATE_DELAY
	bool
	default y

config ARCH_MAY_HAVE_PC_FDC
	bool

config ZONE_DMA
	bool

config ARCH_SUPPORTS_UPROBES
	def_bool y

config ARCH_HAS_DMA_SET_COHERENT_MASK
	bool

config GENERIC_ISA_DMA
	bool

config FIQ
	bool

config NEED_RET_TO_USER
	bool

config ARCH_MTD_XIP
	bool

config ARM_PATCH_PHYS_VIRT
	bool "Patch physical to virtual translations at runtime" if EMBEDDED
	default y
	depends on !XIP_KERNEL && MMU
	help
	  Patch phys-to-virt and virt-to-phys translation functions at
	  boot and module load time according to the position of the
	  kernel in system memory.

	  This can only be used with non-XIP MMU kernels where the base
	  of physical memory is at a 16MB boundary.

	  Only disable this option if you know that you do not require
	  this feature (eg, building a kernel for a single machine) and
	  you need to shrink the kernel to the minimal size.

config NEED_MACH_IO_H
	bool
	help
	  Select this when mach/io.h is required to provide special
	  definitions for this platform.  The need for mach/io.h should
	  be avoided when possible.

config NEED_MACH_MEMORY_H
	bool
	help
	  Select this when mach/memory.h is required to provide special
	  definitions for this platform.  The need for mach/memory.h should
	  be avoided when possible.

config PHYS_OFFSET
	hex "Physical address of main memory" if MMU
	depends on !ARM_PATCH_PHYS_VIRT
	default DRAM_BASE if !MMU
	default 0x00000000 if ARCH_EBSA110 || \
			ARCH_FOOTBRIDGE
	default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
	default 0x20000000 if ARCH_S5PV210
	default 0xc0000000 if ARCH_SA1100
	help
	  Please provide the physical address corresponding to the
	  location of main memory in your system.

config GENERIC_BUG
	def_bool y
	depends on BUG

config PGTABLE_LEVELS
	int
	default 3 if ARM_LPAE
	default 2

menu "System Type"

config MMU
	bool "MMU-based Paged Memory Management Support"
	default y
	help
	  Select if you want MMU-based virtualised addressing space
	  support by paged memory management. If unsure, say 'Y'.

config ARCH_MMAP_RND_BITS_MIN
	default 8

config ARCH_MMAP_RND_BITS_MAX
	default 14 if PAGE_OFFSET=0x40000000
	default 15 if PAGE_OFFSET=0x80000000
	default 16

#
# The "ARM system type" choice list is ordered alphabetically by option
# text.  Please add new entries in the option alphabetic order.
#
choice
	prompt "ARM system type"
	default ARM_SINGLE_ARMV7M if !MMU
	default ARCH_MULTIPLATFORM if MMU

config ARCH_MULTIPLATFORM
	bool "Allow multiple platforms to be selected"
	depends on MMU
	select ARCH_FLATMEM_ENABLE
	select ARCH_SPARSEMEM_ENABLE
	select ARCH_SELECT_MEMORY_MODEL
	select ARM_HAS_SG_CHAIN
	select ARM_PATCH_PHYS_VIRT
	select AUTO_ZRELADDR
	select TIMER_OF
	select COMMON_CLK
	select GENERIC_CLOCKEVENTS
	select GENERIC_IRQ_MULTI_HANDLER
	select HAVE_PCI
	select PCI_DOMAINS_GENERIC if PCI
	select SPARSE_IRQ
	select USE_OF

config ARM_SINGLE_ARMV7M
	bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
	depends on !MMU
	select ARM_NVIC
	select AUTO_ZRELADDR
	select TIMER_OF
	select COMMON_CLK
	select CPU_V7M
	select GENERIC_CLOCKEVENTS
	select NO_IOPORT_MAP
	select SPARSE_IRQ
	select USE_OF

config ARCH_EBSA110
	bool "EBSA-110"
	select ARCH_USES_GETTIMEOFFSET
	select CPU_SA110
	select ISA
	select NEED_MACH_IO_H
	select NEED_MACH_MEMORY_H
	select NO_IOPORT_MAP
	help
	  This is an evaluation board for the StrongARM processor available
	  from Digital. It has limited hardware on-board, including an
	  Ethernet interface, two PCMCIA sockets, two serial ports and a
	  parallel port.

config ARCH_EP93XX
	bool "EP93xx-based"
	select ARCH_SPARSEMEM_ENABLE
	select ARM_AMBA
	imply ARM_PATCH_PHYS_VIRT
	select ARM_VIC
	select AUTO_ZRELADDR
	select CLKDEV_LOOKUP
	select CLKSRC_MMIO
	select CPU_ARM920T
	select GENERIC_CLOCKEVENTS
	select GPIOLIB
	select HAVE_LEGACY_CLK
	help
	  This enables support for the Cirrus EP93xx series of CPUs.

config ARCH_FOOTBRIDGE
	bool "FootBridge"
	select CPU_SA110
	select FOOTBRIDGE
	select GENERIC_CLOCKEVENTS
	select HAVE_IDE
	select NEED_MACH_IO_H if !MMU
	select NEED_MACH_MEMORY_H
	help
	  Support for systems based on the DC21285 companion chip
	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.

config ARCH_IOP32X
	bool "IOP32x-based"
	depends on MMU
	select CPU_XSCALE
	select GPIO_IOP
	select GPIOLIB
	select NEED_RET_TO_USER
	select FORCE_PCI
	select PLAT_IOP
	help
	  Support for Intel's 80219 and IOP32X (XScale) family of
	  processors.

config ARCH_IXP4XX
	bool "IXP4xx-based"
	depends on MMU
	select ARCH_HAS_DMA_SET_COHERENT_MASK
	select ARCH_SUPPORTS_BIG_ENDIAN
	select CPU_XSCALE
	select DMABOUNCE if PCI
	select GENERIC_CLOCKEVENTS
	select GENERIC_IRQ_MULTI_HANDLER
	select GPIO_IXP4XX
	select GPIOLIB
	select HAVE_PCI
	select IXP4XX_IRQ
	select IXP4XX_TIMER
	select NEED_MACH_IO_H
	select USB_EHCI_BIG_ENDIAN_DESC
	select USB_EHCI_BIG_ENDIAN_MMIO
	help
	  Support for Intel's IXP4XX (XScale) family of processors.

config ARCH_DOVE
	bool "Marvell Dove"
	select CPU_PJ4
	select GENERIC_CLOCKEVENTS
	select GENERIC_IRQ_MULTI_HANDLER
	select GPIOLIB
	select HAVE_PCI
	select MVEBU_MBUS
	select PINCTRL
	select PINCTRL_DOVE
	select PLAT_ORION_LEGACY
	select SPARSE_IRQ
	select PM_GENERIC_DOMAINS if PM
	help
	  Support for the Marvell Dove SoC 88AP510

config ARCH_PXA
	bool "PXA2xx/PXA3xx-based"
	depends on MMU
	select ARCH_MTD_XIP
	select ARM_CPU_SUSPEND if PM
	select AUTO_ZRELADDR
	select COMMON_CLK
	select CLKSRC_PXA
	select CLKSRC_MMIO
	select TIMER_OF
	select CPU_XSCALE if !CPU_XSC3
	select GENERIC_CLOCKEVENTS
	select GENERIC_IRQ_MULTI_HANDLER
	select GPIO_PXA
	select GPIOLIB
	select HAVE_IDE
	select IRQ_DOMAIN
	select PLAT_PXA
	select SPARSE_IRQ
	help
	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.

config ARCH_RPC
	bool "RiscPC"
	depends on MMU
	select ARCH_ACORN
	select ARCH_MAY_HAVE_PC_FDC
	select ARCH_SPARSEMEM_ENABLE
	select ARM_HAS_SG_CHAIN
	select CPU_SA110
	select FIQ
	select HAVE_IDE
	select HAVE_PATA_PLATFORM
	select ISA_DMA_API
	select NEED_MACH_IO_H
	select NEED_MACH_MEMORY_H
	select NO_IOPORT_MAP
	help
	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
	  CD-ROM interface, serial and parallel port, and the floppy drive.

config ARCH_SA1100
	bool "SA1100-based"
	select ARCH_MTD_XIP
	select ARCH_SPARSEMEM_ENABLE
	select CLKSRC_MMIO
	select CLKSRC_PXA
	select TIMER_OF if OF
	select COMMON_CLK
	select CPU_FREQ
	select CPU_SA1100
	select GENERIC_CLOCKEVENTS
	select GENERIC_IRQ_MULTI_HANDLER
	select GPIOLIB
	select HAVE_IDE
	select IRQ_DOMAIN
	select ISA
	select NEED_MACH_MEMORY_H
	select SPARSE_IRQ
	help
	  Support for StrongARM 11x0 based boards.

config ARCH_S3C24XX
	bool "Samsung S3C24XX SoCs"
	select ATAGS
	select CLKSRC_SAMSUNG_PWM
	select GENERIC_CLOCKEVENTS
	select GPIO_SAMSUNG
	select GPIOLIB
	select GENERIC_IRQ_MULTI_HANDLER
	select HAVE_S3C2410_I2C if I2C
	select HAVE_S3C_RTC if RTC_CLASS
	select NEED_MACH_IO_H
	select S3C2410_WATCHDOG
	select SAMSUNG_ATAGS
	select USE_OF
	select WATCHDOG
	help
	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
	  Samsung SMDK2410 development board (and derivatives).

config ARCH_OMAP1
	bool "TI OMAP1"
	depends on MMU
	select ARCH_HAS_HOLES_MEMORYMODEL
	select ARCH_OMAP
	select CLKDEV_LOOKUP
	select CLKSRC_MMIO
	select GENERIC_CLOCKEVENTS
	select GENERIC_IRQ_CHIP
	select GENERIC_IRQ_MULTI_HANDLER
	select GPIOLIB
	select HAVE_IDE
	select HAVE_LEGACY_CLK
	select IRQ_DOMAIN
	select NEED_MACH_IO_H if PCCARD
	select NEED_MACH_MEMORY_H
	select SPARSE_IRQ
	help
	  Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)

endchoice

menu "Multiple platform selection"
	depends on ARCH_MULTIPLATFORM

comment "CPU Core family selection"

config ARCH_MULTI_V4
	bool "ARMv4 based platforms (FA526)"
	depends on !ARCH_MULTI_V6_V7
	select ARCH_MULTI_V4_V5
	select CPU_FA526

config ARCH_MULTI_V4T
	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
	depends on !ARCH_MULTI_V6_V7
	select ARCH_MULTI_V4_V5
	select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
		CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
		CPU_ARM925T || CPU_ARM940T)

config ARCH_MULTI_V5
	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
	depends on !ARCH_MULTI_V6_V7
	select ARCH_MULTI_V4_V5
	select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
		CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
		CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)

config ARCH_MULTI_V4_V5
	bool

config ARCH_MULTI_V6
	bool "ARMv6 based platforms (ARM11)"
	select ARCH_MULTI_V6_V7
	select CPU_V6K

config ARCH_MULTI_V7
	bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
	default y
	select ARCH_MULTI_V6_V7
	select CPU_V7
	select HAVE_SMP

config ARCH_MULTI_V6_V7
	bool
	select MIGHT_HAVE_CACHE_L2X0

config ARCH_MULTI_CPU_AUTO
	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
	select ARCH_MULTI_V5

endmenu

config ARCH_VIRT
	bool "Dummy Virtual Machine"
	depends on ARCH_MULTI_V7
	select ARM_AMBA
	select ARM_GIC
	select ARM_GIC_V2M if PCI
	select ARM_GIC_V3
	select ARM_GIC_V3_ITS if PCI
	select ARM_PSCI
	select HAVE_ARM_ARCH_TIMER
	select ARCH_SUPPORTS_BIG_ENDIAN

#
# This is sorted alphabetically by mach-* pathname.  However, plat-*
# Kconfigs may be included either alphabetically (according to the
# plat- suffix) or along side the corresponding mach-* source.
#
source "arch/arm/mach-actions/Kconfig"

source "arch/arm/mach-alpine/Kconfig"

source "arch/arm/mach-artpec/Kconfig"

source "arch/arm/mach-asm9260/Kconfig"

source "arch/arm/mach-aspeed/Kconfig"

source "arch/arm/mach-at91/Kconfig"

source "arch/arm/mach-axxia/Kconfig"

source "arch/arm/mach-bcm/Kconfig"

source "arch/arm/mach-berlin/Kconfig"

source "arch/arm/mach-clps711x/Kconfig"

source "arch/arm/mach-cns3xxx/Kconfig"

source "arch/arm/mach-davinci/Kconfig"

source "arch/arm/mach-digicolor/Kconfig"

source "arch/arm/mach-dove/Kconfig"

source "arch/arm/mach-ep93xx/Kconfig"

source "arch/arm/mach-exynos/Kconfig"

source "arch/arm/mach-footbridge/Kconfig"

source "arch/arm/mach-gemini/Kconfig"

source "arch/arm/mach-highbank/Kconfig"

source "arch/arm/mach-hisi/Kconfig"

source "arch/arm/mach-imx/Kconfig"

source "arch/arm/mach-integrator/Kconfig"

source "arch/arm/mach-iop32x/Kconfig"

source "arch/arm/mach-ixp4xx/Kconfig"

source "arch/arm/mach-keystone/Kconfig"

source "arch/arm/mach-lpc32xx/Kconfig"

source "arch/arm/mach-mediatek/Kconfig"

source "arch/arm/mach-meson/Kconfig"

source "arch/arm/mach-milbeaut/Kconfig"

source "arch/arm/mach-mmp/Kconfig"

source "arch/arm/mach-moxart/Kconfig"

source "arch/arm/mach-mstar/Kconfig"

source "arch/arm/mach-mv78xx0/Kconfig"

source "arch/arm/mach-mvebu/Kconfig"

source "arch/arm/mach-mxs/Kconfig"

source "arch/arm/mach-nomadik/Kconfig"

source "arch/arm/mach-npcm/Kconfig"

source "arch/arm/mach-nspire/Kconfig"

source "arch/arm/plat-omap/Kconfig"

source "arch/arm/mach-omap1/Kconfig"

source "arch/arm/mach-omap2/Kconfig"

source "arch/arm/mach-orion5x/Kconfig"

source "arch/arm/mach-oxnas/Kconfig"

source "arch/arm/mach-picoxcell/Kconfig"

source "arch/arm/mach-prima2/Kconfig"

source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/plat-pxa/Kconfig"

source "arch/arm/mach-qcom/Kconfig"

source "arch/arm/mach-rda/Kconfig"

source "arch/arm/mach-realtek/Kconfig"

source "arch/arm/mach-realview/Kconfig"

source "arch/arm/mach-rockchip/Kconfig"

source "arch/arm/mach-s3c/Kconfig"

source "arch/arm/mach-s5pv210/Kconfig"

source "arch/arm/mach-sa1100/Kconfig"

source "arch/arm/mach-shmobile/Kconfig"

source "arch/arm/mach-socfpga/Kconfig"

source "arch/arm/mach-spear/Kconfig"

source "arch/arm/mach-sti/Kconfig"

source "arch/arm/mach-stm32/Kconfig"

source "arch/arm/mach-sunxi/Kconfig"

source "arch/arm/mach-tango/Kconfig"

source "arch/arm/mach-tegra/Kconfig"

source "arch/arm/mach-u300/Kconfig"

source "arch/arm/mach-uniphier/Kconfig"

source "arch/arm/mach-ux500/Kconfig"

source "arch/arm/mach-versatile/Kconfig"

source "arch/arm/mach-vexpress/Kconfig"

source "arch/arm/mach-vt8500/Kconfig"

source "arch/arm/mach-zx/Kconfig"

source "arch/arm/mach-zynq/Kconfig"

# ARMv7-M architecture
config ARCH_EFM32
	bool "Energy Micro efm32"
	depends on ARM_SINGLE_ARMV7M
	select GPIOLIB
	help
	  Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
	  processors.

config ARCH_LPC18XX
	bool "NXP LPC18xx/LPC43xx"
	depends on ARM_SINGLE_ARMV7M
	select ARCH_HAS_RESET_CONTROLLER
	select ARM_AMBA
	select CLKSRC_LPC32XX
	select PINCTRL
	help
	  Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
	  high performance microcontrollers.

config ARCH_MPS2
	bool "ARM MPS2 platform"
	depends on ARM_SINGLE_ARMV7M
	select ARM_AMBA
	select CLKSRC_MPS2
	help
	  Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
	  with a range of available cores like Cortex-M3/M4/M7.

	  Please, note that depends which Application Note is used memory map
	  for the platform may vary, so adjustment of RAM base might be needed.

# Definitions to make life easier
config ARCH_ACORN
	bool

config PLAT_IOP
	bool
	select GENERIC_CLOCKEVENTS

config PLAT_ORION
	bool
	select CLKSRC_MMIO
	select COMMON_CLK
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config PLAT_ORION_LEGACY
	bool
	select PLAT_ORION

config PLAT_PXA
	bool

config PLAT_VERSATILE
	bool

source "arch/arm/mm/Kconfig"

config IWMMXT
	bool "Enable iWMMXt support"
	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
	help
	  Enable support for iWMMXt context switching at run time if
	  running on a CPU that supports it.

if !MMU
source "arch/arm/Kconfig-nommu"
endif

config PJ4B_ERRATA_4742
	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
	depends on CPU_PJ4B && MACH_ARMADA_370
	default y
	help
	  When coming out of either a Wait for Interrupt (WFI) or a Wait for
	  Event (WFE) IDLE states, a specific timing sensitivity exists between
	  the retiring WFI/WFE instructions and the newly issued subsequent
	  instructions.  This sensitivity can result in a CPU hang scenario.
	  Workaround:
	  The software must insert either a Data Synchronization Barrier (DSB)
	  or Data Memory Barrier (DMB) command immediately after the WFI/WFE
	  instruction

config ARM_ERRATA_326103
	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
	depends on CPU_V6
	help
	  Executing a SWP instruction to read-only memory does not set bit 11
	  of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
	  treat the access as a read, preventing a COW from occurring and
	  causing the faulting task to livelock.

config ARM_ERRATA_411920
	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
	depends on CPU_V6 || CPU_V6K
	help
	  Invalidation of the Instruction Cache operation can
	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
	  It does not affect the MPCore. This option enables the ARM Ltd.
	  recommended workaround.

config ARM_ERRATA_430973
	bool "ARM errata: Stale prediction on replaced interworking branch"
	depends on CPU_V7
	help
	  This option enables the workaround for the 430973 Cortex-A8
	  r1p* erratum. If a code sequence containing an ARM/Thumb
	  interworking branch is replaced with another code sequence at the
	  same virtual address, whether due to self-modifying code or virtual
	  to physical address re-mapping, Cortex-A8 does not recover from the
	  stale interworking branch prediction. This results in Cortex-A8
	  executing the new code sequence in the incorrect ARM or Thumb state.
	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
	  and also flushes the branch target cache at every context switch.
	  Note that setting specific bits in the ACTLR register may not be
	  available in non-secure mode.

config ARM_ERRATA_458693
	bool "ARM errata: Processor deadlock when a false hazard is created"
	depends on CPU_V7
	depends on !ARCH_MULTIPLATFORM
	help
	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
	  erratum. For very specific sequences of memory operations, it is
	  possible for a hazard condition intended for a cache line to instead
	  be incorrectly associated with a different cache line. This false
	  hazard might then cause a processor deadlock. The workaround enables
	  the L1 caching of the NEON accesses and disables the PLD instruction
	  in the ACTLR register. Note that setting specific bits in the ACTLR
	  register may not be available in non-secure mode.

config ARM_ERRATA_460075
	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
	depends on CPU_V7
	depends on !ARCH_MULTIPLATFORM
	help
	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)
	  erratum. Any asynchronous access to the L2 cache may encounter a
	  situation in which recent store transactions to the L2 cache are lost
	  and overwritten with stale memory contents from external memory. The
	  workaround disables the write-allocate mode for the L2 cache via the
	  ACTLR register. Note that setting specific bits in the ACTLR register
	  may not be available in non-secure mode.

config ARM_ERRATA_742230
	bool "ARM errata: DMB operation may be faulty"
	depends on CPU_V7 && SMP
	depends on !ARCH_MULTIPLATFORM
	help
	  This option enables the workaround for the 742230 Cortex-A9
	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
	  between two write operations may not ensure the correct visibility
	  ordering of the two writes. This workaround sets a specific bit in
	  the diagnostic register of the Cortex-A9 which causes the DMB
	  instruction to behave as a DSB, ensuring the correct behaviour of
	  the two writes.

config ARM_ERRATA_742231
	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
	depends on CPU_V7 && SMP
	depends on !ARCH_MULTIPLATFORM
	help
	  This option enables the workaround for the 742231 Cortex-A9
	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
	  Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
	  accessing some data located in the same cache line, may get corrupted
	  data due to bad handling of the address hazard when the line gets
	  replaced from one of the CPUs at the same time as another CPU is
	  accessing it. This workaround sets specific bits in the diagnostic
	  register of the Cortex-A9 which reduces the linefill issuing
	  capabilities of the processor.

config ARM_ERRATA_643719
	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
	depends on CPU_V7 && SMP
	default y
	help
	  This option enables the workaround for the 643719 Cortex-A9 (prior to
	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
	  register returns zero when it should return one. The workaround
	  corrects this value, ensuring cache maintenance operations which use
	  it behave as intended and avoiding data corruption.

config ARM_ERRATA_720789
	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
	depends on CPU_V7
	help
	  This option enables the workaround for the 720789 Cortex-A9 (prior to
	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
	  broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
	  As a consequence of this erratum, some TLB entries which should be
	  invalidated are not, resulting in an incoherency in the system page
	  tables. The workaround changes the TLB flushing routines to invalidate
	  entries regardless of the ASID.

config ARM_ERRATA_743622
	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
	depends on CPU_V7
	depends on !ARCH_MULTIPLATFORM
	help
	  This option enables the workaround for the 743622 Cortex-A9
	  (r2p*) erratum. Under very rare conditions, a faulty
	  optimisation in the Cortex-A9 Store Buffer may lead to data
	  corruption. This workaround sets a specific bit in the diagnostic
	  register of the Cortex-A9 which disables the Store Buffer
	  optimisation, preventing the defect from occurring. This has no
	  visible impact on the overall performance or power consumption of the
	  processor.

config ARM_ERRATA_751472
	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
	depends on CPU_V7
	depends on !ARCH_MULTIPLATFORM
	help
	  This option enables the workaround for the 751472 Cortex-A9 (prior
	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
	  completion of a following broadcasted operation if the second
	  operation is received by a CPU before the ICIALLUIS has completed,
	  potentially leading to corrupted entries in the cache or TLB.

config ARM_ERRATA_754322
	bool "ARM errata: possible faulty MMU translations following an ASID switch"
	depends on CPU_V7
	help
	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
	  r3p*) erratum. A speculative memory access may cause a page table walk
	  which starts prior to an ASID switch but completes afterwards. This
	  can populate the micro-TLB with a stale entry which may be hit with
	  the new ASID. This workaround places two dsb instructions in the mm
	  switching code so that no page table walks can cross the ASID switch.

config ARM_ERRATA_754327
	bool "ARM errata: no automatic Store Buffer drain"
	depends on CPU_V7 && SMP
	help
	  This option enables the workaround for the 754327 Cortex-A9 (prior to
	  r2p0) erratum. The Store Buffer does not have any automatic draining
	  mechanism and therefore a livelock may occur if an external agent
	  continuously polls a memory location waiting to observe an update.
	  This workaround defines cpu_relax() as smp_mb(), preventing correctly
	  written polling loops from denying visibility of updates to memory.

config ARM_ERRATA_364296
	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
	depends on CPU_V6
	help
	  This options enables the workaround for the 364296 ARM1136