From fa0384dc997dad3573f40e3ed9986bae28a8d849 Mon Sep 17 00:00:00 2001
From: "Oliver F. Brown" <oliver.brown@nxp.com>
Date: Fri, 6 May 2022 13:24:36 -0500
Subject: [PATCH] LF-6005: gpu: imx: dpu: framegen: Improve clock handling
The bypass clock and display pixel clock needs to be set for HDMI.
Signed-off-by: Oliver F. Brown <oliver.brown@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
---
drivers/gpu/imx/dpu/dpu-framegen.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/imx/dpu/dpu-framegen.c b/drivers/gpu/imx/dpu/dpu-framegen.c
index aac9efbd4d2c6..50d7d50e1ff87 100644
--- a/drivers/gpu/imx/dpu/dpu-framegen.c
+++ b/drivers/gpu/imx/dpu/dpu-framegen.c
@@ -250,12 +250,16 @@ void framegen_cfg_videomode(struct dpu_framegen *fg, struct drm_display_mode *m,
disp_clock_rate = m->crtc_clock * 1000;
if (encoder_type == DRM_MODE_ENCODER_TMDS) {
- if (side_by_side)
+ clk_set_parent(fg->clk_disp, fg->clk_bypass);
+ if (side_by_side) {
dpu_pxlink_set_mst_addr(dpu, fg->id, fg->id ? 2 : 1);
- else
+ clk_set_rate(fg->clk_bypass, disp_clock_rate / 2);
+ clk_set_rate(fg->clk_disp, disp_clock_rate / 2);
+ } else {
dpu_pxlink_set_mst_addr(dpu, fg->id, 1);
-
- clk_set_parent(fg->clk_disp, fg->clk_bypass);
+ clk_set_rate(fg->clk_bypass, disp_clock_rate);
+ clk_set_rate(fg->clk_disp, disp_clock_rate);
+ }
fg->use_bypass_clk = true;
} else {
--
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