From afc2f90581071da9634e5274063a0feca2ae2e66 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jonas=20H=C3=B6ppner?= <jonas.hoeppner@garz-fricke.com>
Date: Wed, 26 Oct 2022 13:51:53 +0200
Subject: [PATCH] mx8m:sec-dsim: Add message to sec-dsim to print out resulting
 pixel clock rate

BCS 746-001034
---
 drivers/gpu/drm/bridge/sec-dsim.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/bridge/sec-dsim.c b/drivers/gpu/drm/bridge/sec-dsim.c
index 1eb34e7555094..22e5f7e7b5f57 100644
--- a/drivers/gpu/drm/bridge/sec-dsim.c
+++ b/drivers/gpu/drm/bridge/sec-dsim.c
@@ -1013,6 +1013,9 @@ static void sec_mipi_dsim_config_dphy(struct sec_mipi_dsim *dsim)
 
 	key.bit_clk = DIV_ROUND_CLOSEST_ULL(dsim->bit_clk, 1000);
 
+	dev_dbg(dsim->dev, "key.bit_clk %d dsim->bit_clk %d\n",
+			key.bit_clk, dsim->bit_clk);
+
 	/* '1280x720@60Hz' mode with 2 data lanes
 	 * requires special fine tuning for DPHY
 	 * TIMING config according to the tests.
@@ -1035,6 +1038,8 @@ static void sec_mipi_dsim_config_dphy(struct sec_mipi_dsim *dsim)
 			pdata->dphy_timing_cmp);
 	if (WARN_ON(!match))
 		return;
+	dev_info(dsim->dev, "Matching bitrate: %dMHz, resulting pixel clock: %dkHz\n",
+			 match->bit_clk, (match->bit_clk * 1000) / 6);
 
 	phytiming  |= PHYTIMING_SET_M_TLPXCTL(match->lpx)	|
 		      PHYTIMING_SET_M_THSEXITCTL(match->hs_exit);
-- 
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