diff --git a/arch/arm64/boot/dts/seconorth/trizeps8plus.dtsi b/arch/arm64/boot/dts/seconorth/trizeps8plus.dtsi
index cfb48b232769eac012d1797b0acc65d9fc1a5d07..d6cb36cb310f8838672790aa424f6bbe1bfe4be1 100644
--- a/arch/arm64/boot/dts/seconorth/trizeps8plus.dtsi
+++ b/arch/arm64/boot/dts/seconorth/trizeps8plus.dtsi
@@ -106,7 +106,6 @@ trusty-log {
 	};
 };
 
-
 / {
 	memory@40000000 {
 		device_type = "memory";
@@ -117,7 +116,6 @@ reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;
-
 	};
 
 	panel_lvds: panel {
@@ -626,18 +624,6 @@ audiocodec: wm8962@1a {	/* Audio-Codec */
 		SPKVDD2-supply = <&reg_3v3>; // Right Speaker Supply
 	};
 
-#if 0
-	sn65dsi84@2c {
-		status = "disabled";
-		compatible = "ti,sn65dsi84";
-		reg = <0x2c>;
-		enable-gpios =<lvds_en_gpio GPIO_ACTIVE_HIGH>;
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c3_sn65dsi84_en>;
-	};
-#endif
-
 	fpga: tr8fpga@41 {
 		//compatible = "kuk,tr8fpga";
 		compatible = "seco,tr8fpga";
@@ -777,7 +763,6 @@ pinctrl_usb1_vbus: usb1grp {
 			MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR		0x19
 		>;
 	};
-
 };
 
 &usb3_phy1 {
@@ -897,7 +882,7 @@ mipi_csi0_ep: endpoint {
 };
 
 &iomuxc {
-	pinctrl-names = "default";
+
 	pinctrl_ecspi2: ecspi2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82
@@ -933,28 +918,6 @@ ENET_RESET_GPIO1_IO09		0x19
 		>;
 	};
 
-#if 0
-	pinctrl_fec: fecgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x3
-			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
-			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x1f
-			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x1f
-			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x1f
-			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x1f
-			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x91
-			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x91
-			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x91
-			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x91
-			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK		0x1f
-			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK		0x91
-			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
-			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
-			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x19
-		>;
-	};
-#endif
-
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c3
@@ -1181,12 +1144,6 @@ SPIN133_USB1_OC		PAD_GPIO  /* USBOTG_OC, USB1_OC */
 			>;
 	};
 
-#if 0
-	pinctrl_i2c3_sn65dsi84_en: sn65dsi84_iogrp {
-		fsl,pins = < LVDS_EN_GPIO  PAD_GPIO  >; /* Myon internal LVDS Enable and external Pin0-72 */
-	};
-#endif
-
 	pinctrl_sd_vsel: sdvselgrp {
 		fsl,pins = < SD1_VSEL_GPIO1_IO03	PAD_GPIO >;
 	};