From aaf36fc02a66a13e57739d1a6ab7f8d5d28f17ce Mon Sep 17 00:00:00 2001
From: Tobias Poganiuch <tobias.poganiuch@seco.com>
Date: Wed, 6 Dec 2023 10:16:46 +0100
Subject: [PATCH] arm64:dts:tr8p: Clean-up regulator definitions

For trizeps8mini the change in pconcs is disabled for now, until it is
cleaned up too.
---
 arch/arm64/boot/dts/seconorth/pconxs.dtsi     | 24 +++++++++++---
 .../boot/dts/seconorth/trizeps8plus.dtsi      | 32 +++++++++++++++----
 2 files changed, 46 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/seconorth/pconxs.dtsi b/arch/arm64/boot/dts/seconorth/pconxs.dtsi
index 5face82203f75..447cb15a10651 100644
--- a/arch/arm64/boot/dts/seconorth/pconxs.dtsi
+++ b/arch/arm64/boot/dts/seconorth/pconxs.dtsi
@@ -43,7 +43,7 @@ pinctrl_gpio_keys: gpio_keys {
 	pinctrl_backlight_pwm1: pwm-backlight {
 		fsl,pins = < SPIN77_PWM1_OUT	PAD_GPIO >;	/* BACKLIGHT_PWM */
 	};
-		
+
 	pinctrl_backlight_enable: backlight-enable {
 		fsl,pins = < SPIN73_GPIO	    PAD_GPIO >;	/* BACKLIGHT_ENABLE SODIMM Pin 73 */
 	};
@@ -55,14 +55,30 @@ pinctrl_pcie_enable: pcie-enable 	{
 #endif
 
 	pinctrl_usbhost_enable: usbhost-enable 	{
-		fsl,pins = < SPIN129_GPIO		PAD_GPIO >; /* USBH_PWR */
+		fsl,pins = < 
+			SPIN129_GPIO		PAD_GPIO  /* USBH_PWR, USB2_PEN */
+			SPIN131_USB2_OC		PAD_GPIO  /* USBH_OC, USB2_OC */
+			>; 
 	};
 
 	pinctrl_usbotg_enable: usbotg-enable 	{
-		fsl,pins = < SPIN127_GPIO		PAD_GPIO >; /* USBOTG_PWR */
-	};		
+		fsl,pins = < 
+			SPIN127_GPIO		PAD_GPIO  /* USBOTG_PWR, USB1_PEN */
+			SPIN133_USB1_OC		PAD_GPIO  /* USBOTG_OC, USB1_OC */
+			>;
+	};
 };
 
+#if TRIZEPS8PLUS
+/* TODO: This guard should be remove when the tr8mini is cleaned up
+         But the whole regulator chain needs some rework too
+*/
+/* Supply for the trizeps module */
+&reg_vsys {
+	vin-supply = <&reg_vin_fused>;
+};
+#endif
+
 / {
 	reg_vin_fused: vin_fused {
 		compatible = "regulator-fixed";
diff --git a/arch/arm64/boot/dts/seconorth/trizeps8plus.dtsi b/arch/arm64/boot/dts/seconorth/trizeps8plus.dtsi
index f0fdb34dbc072..51691d26ce8d8 100644
--- a/arch/arm64/boot/dts/seconorth/trizeps8plus.dtsi
+++ b/arch/arm64/boot/dts/seconorth/trizeps8plus.dtsi
@@ -147,11 +147,12 @@ phy_reset: phy-reset {
 		#reset-cells = <0>;
 	};
 
+	/* Input supply of the trizeps module */
 	reg_vsys: regulator-vsys {
 		compatible = "regulator-fixed";
 		regulator-name = "VSYS";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
 		regulator-always-on;
 	};
 
@@ -173,20 +174,35 @@ reg_3v3: 3v3 {
 		vin-supply = <&reg_vsys>;
 	};
 
-	reg_usdhc1_vmmc: usdhc1_vmmc {
+	reg_usdhc1_vmmc: regulator-usdhc1-vmmc {
 		compatible = "regulator-fixed";
 		regulator-name = "VMMC_USDHC1";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
-		enable-active-high;
+		regulator-always-on;
+		vin-supply = <&reg_vin_fused>;
 	};
 
-	reg_usdhc2_vmmc: regulator-usdhc2 {
+	reg_usdhc1_vqmmc: regulator-usdhc1-vqmmc {
+		compatible = "regulator-gpio";
+		regulator-name = "VQMMC_USDHC1";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_sd_vsel>;
+		gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+		gpio-states = <1>;
+		states = <1800000 1>, <3300000 0>;
+		vin-supply = <&reg_vin_fused>;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
 		compatible = "regulator-fixed";
 		regulator-name = "VMMC_USDHC2";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
-		enable-active-high;
+		regulator-always-on;
+		vin-supply = <&reg_vin_fused>;
 	};
 
 #if defined(TRIZEPS8MINI_BT_SCO_XTOR) && (TRIZEPS8MINI_BT_SCO_XTOR==1)
@@ -1073,6 +1089,10 @@ pinctrl_i2c3_sn65dsi84_en: sn65dsi84_iogrp {
 	};
 #endif
 
+	pinctrl_sd_vsel: sdvselgrp {
+		fsl,pins = < SD1_VSEL_GPIO1_IO03	PAD_GPIO >;
+	};
+
 	pinctrl_flexcan1: flexcan1grp {
 		fsl,pins = <
 			SPIN97_CAN1_RX	0x00000106
-- 
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