From 6cdb47091cffcf134ea167a7db5604dc495fa587 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jonas=20H=C3=B6ppner?= <jonas.hoeppner@garz-fricke.com>
Date: Thu, 27 Oct 2022 10:17:39 +0200
Subject: [PATCH] seco-mx8mm: Allow to specify the VIDIO_PLL1_RATE as define
This is a bit hacky but currently I don't know a better solution.
Though the doc say assigned-clock-parents may not be used to set clock rates
if there are multiple consumers this is used here widely.
( see Documentation/devicetree/bindings/clock/clock-bindings.txt line 164)
To allow to change this in devicetree using this file, this macro is
introduced, using the default value from before as default.
BCS 746-001034
(cherry picked from commit 89848b5e14a04f548dd17b494225bdbb488b7ccd)
---
arch/arm64/boot/dts/keithkoep/imx8mm.dtsi | 24 +++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/keithkoep/imx8mm.dtsi b/arch/arm64/boot/dts/keithkoep/imx8mm.dtsi
index 6be6f1e66d11d..af77dd7c4cc09 100755
--- a/arch/arm64/boot/dts/keithkoep/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/keithkoep/imx8mm.dtsi
@@ -13,6 +13,16 @@
#include "imx8mm-pinfunc.h"
+/* Though the doc say assigned-clock-parents may not be used to set clock rates
+ if there are multiple consumers this is used here widely.
+ ( see Documentation/devicetree/bindings/clock/clock-bindings.txt line 164)
+ To allow to change this in devicetree using this file, this macro is
+ introduced, using the default value from before as default.
+*/
+#ifndef VIDEO_PLL1_RATE
+#define VIDEO_PLL1_RATE 594000000
+#endif
+
/ {
compatible = "fsl,imx8mm";
interrupt-parent = <&gic>;
@@ -743,7 +753,7 @@ clk: clock-controller@30380000 {
<400000000>,
<400000000>,
<750000000>,
- <594000000>,
+ <VIDEO_PLL1_RATE>,
<393216000>,
<361267200>;
};
@@ -1137,7 +1147,7 @@ lcdif: lcdif@32e00000 {
assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
<&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_SYS_PLL1_800M>;
- assigned-clock-rate = <594000000>, <500000000>, <200000000>;
+ assigned-clock-rate = <VIDEO_PLL1_RATE>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
lcdif-gpr = <&dispmix_gpr>;
resets = <&lcdif_resets>;
@@ -1163,16 +1173,10 @@ mipi_dsi: mipi_dsi@32e10000 {
clock-names = "cfg", "pll-ref";
assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>;
-#if 0
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
- <&clk IMX8MM_CLK_24M>;
- assigned-clock-rates = <266000000>, <12000000>;
-#else
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
- <&clk IMX8MM_VIDEO_PLL1_OUT>;
- assigned-clock-rates = <266000000>, <594000000>;
+ <&clk IMX8MM_VIDEO_PLL1_OUT>;
+ assigned-clock-rates = <266000000>, <VIDEO_PLL1_RATE>;
pref-rate = <11880>;
-#endif
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
dsi-gpr = <&dispmix_gpr>;
resets = <&mipi_dsi_resets>;
--
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