From 289fbdd42d8c4f15e40b5b220e3dc7163db34f06 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jonas=20H=C3=B6ppner?= <jonas.hoeppner@garz-fricke.com>
Date: Wed, 22 Dec 2021 15:22:32 +0100
Subject: [PATCH] imx8mp-ldb: remove hardcoded pixel clock overwrite

The imx8mp ldb driver had an hardcoded overwrite for the pixelclock as
the video_pll is not able to generate all needed frequencies.
But the hardcoded value only fits to one mode, probably used on the
EVK.
Removing this override leads to a pixelclock that may be generated with
a devider from the PLL, which ends up with a frquency much closer to what
is expected.

Also it is not the ldb clock but the lcdif clock used for this, so this
seems to be the wrong place for modifying the clock anyway.

BCS 746-000502

(cherry picked from commit 86df943de1f70cb4fdce4b08123221b982e0d0aa)
---
 drivers/gpu/drm/imx/imx8mp-ldb.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/imx/imx8mp-ldb.c b/drivers/gpu/drm/imx/imx8mp-ldb.c
index 9f10f92a86714..5751e1aa4365e 100644
--- a/drivers/gpu/drm/imx/imx8mp-ldb.c
+++ b/drivers/gpu/drm/imx/imx8mp-ldb.c
@@ -194,14 +194,26 @@ imx8mp_ldb_encoder_atomic_check(struct drm_encoder *encoder,
 		return -EINVAL;
 	}
 
+	/* Removed as the PLL might only have few PLL frequency
+	   points, but the devider allows frequencies much closer
+	   to the configured one, as just selecting one pixelclock
+	   here.
+	   If this would be needed it is also not clear
+	   why this should be done here, as the related clock
+	   is the lcdif*_pixel_clk on mx8mp, though I guess it should be done in
+
+	   lcdifv3_crtc_atomic_check
+	   */
 	/*
 	 * Due to limited video PLL frequency points on i.MX8mp,
 	 * we do mode fixup here in case any mode is unsupported.
 	 */
+	/*
 	if (ldb->dual)
 		mode->clock = mode->clock > 100000 ? 148500 : 74250;
 	else
 		mode->clock = 74250;
+	*/
 
 	return 0;
 }
-- 
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