diff --git a/drivers/gpu/drm/imx/imx8mp-ldb.c b/drivers/gpu/drm/imx/imx8mp-ldb.c
index 9f10f92a867143990c65b0f59702bf0bd8de5f6c..5751e1aa4365e815fd700d41d8ca6204d370655f 100644
--- a/drivers/gpu/drm/imx/imx8mp-ldb.c
+++ b/drivers/gpu/drm/imx/imx8mp-ldb.c
@@ -194,14 +194,26 @@ imx8mp_ldb_encoder_atomic_check(struct drm_encoder *encoder,
 		return -EINVAL;
 	}
 
+	/* Removed as the PLL might only have few PLL frequency
+	   points, but the devider allows frequencies much closer
+	   to the configured one, as just selecting one pixelclock
+	   here.
+	   If this would be needed it is also not clear
+	   why this should be done here, as the related clock
+	   is the lcdif*_pixel_clk on mx8mp, though I guess it should be done in
+
+	   lcdifv3_crtc_atomic_check
+	   */
 	/*
 	 * Due to limited video PLL frequency points on i.MX8mp,
 	 * we do mode fixup here in case any mode is unsupported.
 	 */
+	/*
 	if (ldb->dual)
 		mode->clock = mode->clock > 100000 ? 148500 : 74250;
 	else
 		mode->clock = 74250;
+	*/
 
 	return 0;
 }