From 10f71c8f743f0b855ce043c6abd2af4a3c52a987 Mon Sep 17 00:00:00 2001
From: Tobias Poganiuch <tobias.poganiuch@seco.com>
Date: Fri, 16 Aug 2024 11:36:20 +0200
Subject: [PATCH] arm64:dts: Reduce drive-strength for USDHC2
The signal over-/undershoots to much with the drive-strength of x6.
---
arch/arm64/boot/dts/seco/include/mv.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/seco/include/mv.dtsi b/arch/arm64/boot/dts/seco/include/mv.dtsi
index d6bb53c3217f2..4d1066e32c941 100644
--- a/arch/arm64/boot/dts/seco/include/mv.dtsi
+++ b/arch/arm64/boot/dts/seco/include/mv.dtsi
@@ -121,3 +121,27 @@ rs485_de {
output-high;
};
};
+
+&pinctrl_usdhc2_100mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+};
+
+&pinctrl_usdhc2_200mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+};
--
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