From aac44baf6cf75188c56ae316e39888889c565ec5 Mon Sep 17 00:00:00 2001
From: Clemens Terasa <clemens.terasa@garz-fricke.com>
Date: Wed, 20 Jul 2022 12:42:13 +0200
Subject: [PATCH] arm: dts: NALLINO: Activate SSC and assign PLL2_PFD1 as LCDIF
clock parent
In order to jitter the Display the LCDIF clock need to be derived from
the PLL2 which supports Spread Spectrum clocking.
With this and the OS and RAM validation tests Spread Spectrum can be
generally used. Thus enable it by default.
BCS 746-000990
---
arch/arm/boot/dts/garzfricke/imx6ull-nallino.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/garzfricke/imx6ull-nallino.dts b/arch/arm/boot/dts/garzfricke/imx6ull-nallino.dts
index c4ea94c32c4d0..d0a20f65e0008 100644
--- a/arch/arm/boot/dts/garzfricke/imx6ull-nallino.dts
+++ b/arch/arm/boot/dts/garzfricke/imx6ull-nallino.dts
@@ -165,7 +165,7 @@ spreadspectrum: spreadspectrum {
step = <1>;
stop = <250>;
denom = <400>;
- enabled = <0>;
+ enabled = <1>;
};
sound-mqs {
@@ -796,7 +796,7 @@ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 /*PF1550 INT*/
&lcdif {
assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
- assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
--
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