From cc78d6b16a6853a3f6c014a6173df41d80f65a35 Mon Sep 17 00:00:00 2001
From: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Date: Thu, 8 Dec 2011 11:59:03 +0530
Subject: [PATCH] ath9k_hw: Fix handling of MCI interrupt
in my previous patches of handling MCI interrupt I overlooked
the case of interrupt status/mask variable being zeroed out in
the below code, so ath_isr does not cache the MCI interrupt
in the intrstatus. finally MCI interrupt handling won't be
handled in ath9k_tasklet for the scheduled interrupts.
Fix this by moving the MCI interrupt code in the appropriate
position in ar9003_hw_get_isr
Cc: Wilson Tsao <wtsao@qca.qualcomm.com>
Cc: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
---
drivers/net/wireless/ath/ath9k/ar9003_mac.c | 57 +++++++++++----------
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index 508c2022ea9ff..631fe4f2e495e 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -187,34 +187,6 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
isr = REG_READ(ah, AR_ISR);
}
- if (async_cause & AR_INTR_ASYNC_MASK_MCI) {
- u32 raw_intr, rx_msg_intr;
-
- rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
- raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW);
-
- if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef))
- ath_dbg(common, ATH_DBG_MCI,
- "MCI gets 0xdeadbeef during MCI int processing"
- "new raw_intr=0x%08x, new rx_msg_raw=0x%08x, "
- "raw_intr=0x%08x, rx_msg_raw=0x%08x\n",
- raw_intr, rx_msg_intr, mci->raw_intr,
- mci->rx_msg_intr);
- else {
- mci->rx_msg_intr |= rx_msg_intr;
- mci->raw_intr |= raw_intr;
- *masked |= ATH9K_INT_MCI;
-
- if (rx_msg_intr & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO)
- mci->cont_status =
- REG_READ(ah, AR_MCI_CONT_STATUS);
-
- REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr);
- REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr);
- ath_dbg(common, ATH_DBG_MCI, "AR_INTR_SYNC_MCI\n");
-
- }
- }
sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
@@ -326,6 +298,35 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
ar9003_hw_bb_watchdog_read(ah);
}
+ if (async_cause & AR_INTR_ASYNC_MASK_MCI) {
+ u32 raw_intr, rx_msg_intr;
+
+ rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
+ raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW);
+
+ if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef))
+ ath_dbg(common, ATH_DBG_MCI,
+ "MCI gets 0xdeadbeef during MCI int processing"
+ "new raw_intr=0x%08x, new rx_msg_raw=0x%08x, "
+ "raw_intr=0x%08x, rx_msg_raw=0x%08x\n",
+ raw_intr, rx_msg_intr, mci->raw_intr,
+ mci->rx_msg_intr);
+ else {
+ mci->rx_msg_intr |= rx_msg_intr;
+ mci->raw_intr |= raw_intr;
+ *masked |= ATH9K_INT_MCI;
+
+ if (rx_msg_intr & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO)
+ mci->cont_status =
+ REG_READ(ah, AR_MCI_CONT_STATUS);
+
+ REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr);
+ REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr);
+ ath_dbg(common, ATH_DBG_MCI, "AR_INTR_SYNC_MCI\n");
+
+ }
+ }
+
if (sync_cause) {
if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
--
GitLab