Integrate meta-seco-imx/u-boot-seco-imx/seco_lf_v2021.04_d18-video (!451) · Merge requests · Clea OS / seco-manifest

refclk-frequency
- type: u32
- value: should be 12, 19.2, 26, 27 or 38.4 MHz
- description: if present DP PLL is derived from REFCLK otherwise DP PLL is derived from DACP/N
si-result
- type: (u32 u32) tuple array
- description: fine-tune swing and pre-emphasis for Signal Integrity
test-mode
- type: boolean
- description: generate video test pattern
dump-regs
- type: boolean
- description: dump bridge registers

REFERENCE: https://git.seco.com/edgehog/bsp/nxp/linux-seco-imx/-/blob/seco_lf-5.10.y/drivers/gpu/drm/bridge/seco-sn65dsi86.c https://git.seco.com/edgehog/bsp/nxp/linux-seco-imx/-/blob/6c76c0eb031f0a590c03da7381c0251ca783c585/drivers/gpu/drm/bridge/ti-sn65dsi86.c

Commit: edgehog/bsp/nxp/u-boot-seco-imx@edf75fd4

[D18][ENV] set SPLASHIMAGE_ADDR

Commit: edgehog/bsp/nxp/u-boot-seco-imx@f745eb79

[D18][DTS] add LVDS FHD dual-channel video support

on CSB79REVB: panel AUO P215HVN01.0 + CV1235/750REVB (LVDS CN14: switch SW6 1-3 and 2-4 position OFF, jumper CN18 position 2-3 and CN19 position 1-2)

Commit: edgehog/bsp/nxp/u-boot-seco-imx@dcdf2527

[D18][BOARD] set LCD0 VDD, BKL enable

Commit: edgehog/bsp/nxp/u-boot-seco-imx@505a1a47

[D18][DEFCONFIG] add LVDS display support

Commit: edgehog/bsp/nxp/u-boot-seco-imx@fcbc99a0

[D18][BOARD] fix pad mux configuration

Commit: edgehog/bsp/nxp/u-boot-seco-imx@c026dbdc

[D18][DTS][BOARD] clear reference board peripherals

Commit: edgehog/bsp/nxp/u-boot-seco-imx@3c60a494

[i.MX8MP][DRIVER] configure display clk tree

For the clock tree to be able to set up the required LVDS and eDP(DSI to eDP bridge) display clock frequencies we need to configure the entire path, starting from the PLL. It has to be noted that the i.MX8MP SoC has limited supported PLL frequency points, so to support a new panel that has different clock rate than others it may be needed to add a new point to the PLL table.

add frequency 1039.5M to PLL table
set VIDEO_PLL to 1039.5M
set AXI_CLK to 500M from SYSTEM_PLL2
set MIPI_PHY1_REF_CLK to 12M from OSC_24M (for dsi)
set LDB_CLK to 519.75M from VIDEO_PLL (for lvds)
configure clk tree differently depending on display:
- lcdif1 (for dsi): set DISP1_PIX_CLK to 173.25M from VIDEO_PLL
- lcdif2 (for lvds): set DISP2_CLK to 148.5M from VIDEO_PLL

Commit: edgehog/bsp/nxp/u-boot-seco-imx@ad833211

[i.MX8MP][D18][DTS] add i.MX8MP LVDS nodes

REFERENCE: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Add-i-MX8MP-LVDS-driver-in-uboot/ta-p/1434826

Commit: edgehog/bsp/nxp/u-boot-seco-imx@176ee96c

[DRIVER] video: imx: add i.MX8MP LVDS bridge driver

Supported modes:

single channel: LVDS channel 0 only
dual channel: LVDS channel 0, 1 together

Properties:

data-mapping
- type: string
- value: should be "spwg" or "jeida" defaults to "spwg"
data-width
- type: u32
- value: should be <18> or <24> defaults to <18>
dual-channel
- type: boolean

REFERENCE: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Add-i-MX8MP-LVDS-driver-in-uboot/ta-p/1434826

Commit: edgehog/bsp/nxp/u-boot-seco-imx@749af60e

LFU-247-2 video: sec_dsim: Update DPHY PLL PMS and DPHY timing settings

Change to calculate the PLL PMS at runtime for bit_clk, not use hardcode value for 1080p@60 only.

Also update the DPHY timing settings to follow kernel to select values from a pre-setting table.

Signed-off-by: Ye Li ye.li@nxp.com Reviewed-by: Peng Fan peng.fan@nxp.com (cherry picked from commit a2ca81dc77f1e79e4fe6a0369b9f702b2829e8be)

Commit: edgehog/bsp/nxp/u-boot-seco-imx@747fff31

LFU-247-1 imx8m: clock: Add function to get DSI PHY reference clock rate

The D-PHY ref clock source is configurable. We need to know the reference clock rate for D-PHY PLL calculation.

Signed-off-by: Ye Li ye.li@nxp.com Reviewed-by: Peng Fan peng.fan@nxp.com (cherry picked from commit 2560cd096e54d21d5b68fd3cb70e4d3140854bc3)

Integrate meta-seco-imx/u-boot-seco-imx/seco_lf_v2021.04_d18-video

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