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Commit 18c1beba authored by Natalia Kovalenko's avatar Natalia Kovalenko Committed by Alessandro Pecugi
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[C31] [DTS] Assign parent clock to dclk_source 

When RK3399_TWO_PLL_FOR_VOP defined that is needed for dual display
support, where two PLLs are required, dclk_vop0 exclusively occupies
the CPLL, and dclk_vop1 exclusively occupies the VPLL.

Add include rk3399-vop-clk-set.dtsi indirectly by creating
seco-rk3399-vop-clk-set.dtsi, because we have to overwrite PLL_NPLL clock
frequency to obtain 125MHz clock rate for GMAC.
parent 1d4ade56
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arch/arm64/boot/dts/seco/seco-rk3399-c31.dtsi
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......@@ -15,6 +15,7 @@
#include "../rockchip/rk3399.dtsi"
#include "../rockchip/rk3399-opp.dtsi"
#include "seco-rk3399-vop-clk-set.dtsi"
/ {
model = "Rockchip RK3399 SECO Board (C31)";
......
arch/arm64/boot/dts/seco/seco-rk3399-vop-clk-set.dtsi 0 → 100644
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View file @ 18c1beba
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "../rockchip/rk3399-vop-clk-set.dtsi"
#ifdef RK3399_TWO_PLL_FOR_VOP
&vopb {
assigned-clocks = <&cru DCLK_VOP0_DIV>;
assigned-clock-parents = <&cru PLL_CPLL>;
};
&vopl {
assigned-clocks = <&cru DCLK_VOP1_DIV>;
assigned-clock-parents = <&cru PLL_VPLL>;
};
&cru {
assigned-clocks =
<&cru ACLK_PERIHP>, <&cru ACLK_PERILP0>,
<&cru HCLK_PERILP1>, <&cru SCLK_SDMMC>,
<&cru ACLK_EMMC>, <&cru ACLK_CENTER>,
<&cru HCLK_SD>, <&cru SCLK_VDU_CA>,
<&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>,
<&cru FCLK_CM0S>, <&cru ACLK_CCI>,
<&cru PCLK_ALIVE>, <&cru ACLK_GMAC>,
<&cru SCLK_CS>, <&cru SCLK_CCI_TRACE>,
<&cru ARMCLKL>, <&cru ARMCLKB>,
<&cru PLL_NPLL>, <&cru ACLK_GPU>,
<&cru PLL_GPLL>, <&cru ACLK_PERIHP>,
<&cru HCLK_PERIHP>, <&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru HCLK_PERILP1>,
<&cru PCLK_PERILP1>, <&cru SCLK_I2C1>,
<&cru SCLK_I2C2>, <&cru SCLK_I2C3>,
<&cru SCLK_I2C5>, <&cru SCLK_I2C6>,
<&cru SCLK_I2C7>, <&cru SCLK_SPI0>,
<&cru SCLK_SPI1>, <&cru SCLK_SPI2>,
<&cru SCLK_SPI4>, <&cru SCLK_SPI5>,
<&cru ACLK_GIC>, <&cru ACLK_ISP0>,
<&cru ACLK_ISP1>, <&cru SCLK_VOP0_PWM>,
<&cru SCLK_VOP1_PWM>, <&cru PCLK_EDP>,
<&cru ACLK_HDCP>, <&cru ACLK_VIO>,
<&cru HCLK_SD>, <&cru SCLK_CRYPTO0>,
<&cru SCLK_CRYPTO1>, <&cru SCLK_EMMC>,
<&cru ACLK_EMMC>, <&cru ACLK_CENTER>,
<&cru ACLK_IEP>, <&cru ACLK_RGA>,
<&cru SCLK_RGA_CORE>, <&cru ACLK_VDU>,
<&cru ACLK_VCODEC>, <&cru PCLK_DDR>,
<&cru ACLK_GMAC>, <&cru SCLK_VDU_CA>,
<&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>,
<&cru FCLK_CM0S>, <&cru ACLK_CCI>,
<&cru PCLK_ALIVE>, <&cru SCLK_CS>,
<&cru SCLK_CCI_TRACE>, <&cru ACLK_VOP0>,
<&cru HCLK_VOP0>, <&cru ACLK_VOP1>,
<&cru HCLK_VOP1>;
assigned-clock-rates =
<75000000>, <50000000>,
<50000000>, <50000000>,
<50000000>, <100000000>,
<50000000>, <150000000>,
<150000000>, <150000000>,
<50000000>, <150000000>,
<50000000>, <100000000>,
<75000000>, <75000000>,
<816000000>, <816000000>,
<500000000>, <200000000>,
<800000000>, <150000000>,
<75000000>, <37500000>,
<300000000>, <100000000>,
<50000000>, <100000000>,
<50000000>, <100000000>,
<100000000>, <100000000>,
<100000000>, <100000000>,
<100000000>, <50000000>,
<50000000>, <50000000>,
<50000000>, <50000000>,
<200000000>, <400000000>,
<400000000>, <100000000>,
<100000000>, <100000000>,
<400000000>, <400000000>,
<200000000>, <100000000>,
<200000000>, <200000000>,
<100000000>, <400000000>,
<400000000>, <400000000>,
<400000000>, <300000000>,
<400000000>, <200000000>,
<400000000>, <300000000>,
<300000000>, <300000000>,
<300000000>, <600000000>,/* aclk_cci */
<100000000>, <150000000>,
<150000000>, <400000000>,
<100000000>, <400000000>,
<100000000>;
};
#endif
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