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Commit fbf36d6c authored by Gianfranco Mariotti's avatar Gianfranco Mariotti
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[C26][C43] allow board boot by removing power conflicts, refactoring

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arch/arm/mach-imx/imx8/Kconfig
+ 2
− 2
View file @ fbf36d6c
......@@ -103,7 +103,7 @@ config TARGET_IMX8QM_MEK
select SPL_CRYPTO_SUPPORT if SPL
config TARGET_SECO_IMX8QM_C26
bool "Support i.MX8QM SECO C26 Smark module"
bool "Support i.MX8QM SECO C26 Q7 module"
select BOARD_LATE_INIT
select IMX8QM
select FSL_CAAM
......@@ -112,7 +112,7 @@ config TARGET_SECO_IMX8QM_C26
select SPL_CRYPTO_SUPPORT if SPL
config TARGET_SECO_IMX8QM_C43
bool "Support i.MX8QM SECO C43 Smark module"
bool "Support i.MX8QM SECO C43 board"
select BOARD_LATE_INIT
select IMX8QM
select FSL_CAAM
......
board/seco/imx8mq_c12/env_conf.h
+ 2
− 2
View file @ fbf36d6c
......@@ -77,7 +77,7 @@ size_t filesystem_dev_imx8_size = sizeof( filesystem_dev_imx8_list ) / sizeof( f
/* LVDSx1, HDMI */
video_mode_t video_mode_list_cfg [] = {
video_mode_t video_mode_list [] = {
{
/* NO DISPLAY */
.label = SECO_VIDEO_LABEL_NONE,
......@@ -131,7 +131,7 @@ video_mode_t video_mode_list_cfg [] = {
};
size_t video_mode_size_cfg = sizeof( video_mode_list_cfg ) / sizeof( video_mode_list_cfg[0] );
size_t video_mode_size = sizeof( video_mode_list ) / sizeof( video_mode_list[0] );
#ifdef CONFIG_OF_LIBFDT_OVERLAY
......
board/seco/imx8mq_c12/imx8mq_c12.c
+ 2
− 2
View file @ fbf36d6c
......@@ -330,8 +330,8 @@ int board_late_init(void)
gd->bsp_sources.filesystem_dev_num = filesystem_dev_imx8_size;
#ifdef CONFIG_OF_LIBFDT_OVERLAY
gd->boot_setup.video_mode_list = video_mode_list_cfg;
gd->boot_setup.video_mode_num = video_mode_size_cfg;
gd->boot_setup.video_mode_list = video_mode_list;
gd->boot_setup.video_mode_num = video_mode_size;
gd->boot_setup.overlay_peripheral_list = overlay_peripheral_list;
gd->boot_setup.overlay_peripheral_num = overlay_peripheral_size;
......
board/seco/imx8mq_c20/env_conf.h
+ 2
− 2
View file @ fbf36d6c
......@@ -72,7 +72,7 @@ size_t filesystem_dev_imx8_size = sizeof( filesystem_dev_imx8_list ) / sizeof( f
/* LVDSx1, eDP */
video_mode_t video_mode_list_cfg [] = {
video_mode_t video_mode_list [] = {
{
/* NO DISPLAY */
.label = SECO_VIDEO_LABEL_NONE,
......@@ -116,7 +116,7 @@ video_mode_t video_mode_list_cfg [] = {
};
size_t video_mode_size_cfg = sizeof( video_mode_list_cfg ) / sizeof( video_mode_list_cfg[0] );
size_t video_mode_size = sizeof( video_mode_list ) / sizeof( video_mode_list[0] );
#ifdef CONFIG_OF_LIBFDT_OVERLAY
......
board/seco/imx8mq_c20/imx8mq_c20.c
+ 2
− 2
View file @ fbf36d6c
......@@ -386,8 +386,8 @@ int board_late_init(void)
gd->bsp_sources.filesystem_dev_num = filesystem_dev_imx8_size;
#ifdef CONFIG_OF_LIBFDT_OVERLAY
gd->boot_setup.video_mode_list = video_mode_list_cfg;
gd->boot_setup.video_mode_num = video_mode_size_cfg;
gd->boot_setup.video_mode_list = video_mode_list;
gd->boot_setup.video_mode_num = video_mode_size;
gd->boot_setup.overlay_peripheral_list = overlay_peripheral_list;
gd->boot_setup.overlay_peripheral_num = overlay_peripheral_size;
......
board/seco/imx8qm_c26/MAINTAINERS
+ 1
− 0
View file @ fbf36d6c
TARGET_SECO_IMX8QM_C26
M: Davide Cardillo <davide.cardillo@seco.com>
M: Gianfranco Mariotti <gianfranco.mariotti@seco.com>
S: Maintained
F: board/seco/imx8qm_c26/env_conf.h
F: board/seco/imx8qm_c26/imx8qm_c26.c
......
board/seco/imx8qm_c26/env_conf.h
+ 4
− 4
View file @ fbf36d6c
......@@ -97,7 +97,7 @@ size_t filesystem_dev_imx8_size = sizeof( filesystem_dev_imx8_list ) / sizeof( f
/* LVDSx1, eDP */
video_mode_t video_mode_list_cfg_a1 [] = {
video_mode_t video_mode_list_a1 [] = {
{
/* NO DISPLAY */
.label = SECO_VIDEO_LABEL_NONE,
......@@ -181,12 +181,12 @@ video_mode_t video_mode_list_cfg_a1 [] = {
};
size_t video_mode_size_cfg_a1 = sizeof( video_mode_list_cfg_a1 ) / sizeof( video_mode_list_cfg_a1[0] );
size_t video_mode_size_a1 = sizeof( video_mode_list_a1 ) / sizeof( video_mode_list_a1[0] );
/* LVDSx1, eDP */
video_mode_t video_mode_list_cfg_a2 [] = {
video_mode_t video_mode_list_a2 [] = {
{
/* NO DISPLAY */
.label = SECO_VIDEO_LABEL_NONE,
......@@ -223,7 +223,7 @@ video_mode_t video_mode_list_cfg_a2 [] = {
};
size_t video_mode_size_cfg_a2 = sizeof( video_mode_list_cfg_a2 ) / sizeof( video_mode_list_cfg_a2[0] );
size_t video_mode_size_a2 = sizeof( video_mode_list_a2 ) / sizeof( video_mode_list_a2[0] );
......
board/seco/imx8qm_c26/imx8qm_c26.c
+ 53
− 292
View file @ fbf36d6c
......@@ -10,6 +10,7 @@
#include <init.h>
#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <linux/delay.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <asm/gpio.h>
......@@ -22,14 +23,12 @@
#include <asm/arch/sys_proto.h>
#include "../common/tcpc.h"
#include "command.h"
#include "../common/proto_seco.h"
#include "seco/seco_env_gd.h"
#include "imx8qm_c26.h"
#include "strap_cfg.h"
#include "asm/arch-imx8/imx8qm_lpcg.h"
#include "asm/arch-imx8/lpcg.h"
#include "dt-bindings/soc/imx8_pd.h"
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -51,9 +50,6 @@ DECLARE_GLOBAL_DATA_PTR;
static void setup_iomux_uart( void ) {
imx8_iomux_setup_multiple_pads( uart0_pads, ARRAY_SIZE( uart0_pads ) );
}
/* __________________________________________________________________________
* |__________________________________________________________________________|
*/
/* __________________________________________________________________________
* | |
......@@ -62,15 +58,15 @@ static void setup_iomux_uart( void ) {
*/
#define BOOT_VALIDATE IMX_GPIO_NR(2,31)
static void send_boot_validate( void ) {
boot_validate (BOOT_VALIDATE, SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL));
}
/* __________________________________________________________________________
* | |
* | DRAM |
* |__________________________________________________________________________|
*/
#define PHYS_DRAM_IS_1GB 0x40000000
#define PHYS_DRAM_IS_2GB 0x80000000
#define PHYS_DRAM_IS_3GB 0xc0000000
......@@ -115,8 +111,6 @@ void board_mem_get_layout(u64 *phys_sdram_1_start,
*phys_sdram_2_size = sdram_size;
}
/* __________________________________________________________________________
* | |
* | BOOT DEVICE |
......@@ -129,11 +123,10 @@ boot_mem_dev_t boot_mem_dev_list[SECO_NUM_BOOT_DEV] = {
};
int usdhc_devno[4] = { BOARD_BOOT_ID_EMMC, BOARD_BOOT_ID_SD, BOARD_BOOT_ID_SD_EXT, -1};
/* __________________________________________________________________________
* |__________________________________________________________________________|
*/
int board_early_init_f(void)
{
sc_pm_clock_rate_t rate = SC_80MHZ;
......@@ -163,64 +156,27 @@ int board_early_init_f(void)
}
#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20)
#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24)
#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23)
#define IMX8_RST_HUB IMX_GPIO_NR(4, 3)
#define USB_HC_SEL IMX_GPIO_NR(4, 6)
#define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT))
static iomux_cfg_t board_pcie_pins[] = {
SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
};
static iomux_cfg_t board_gpios[] = {
SC_P_USB_SS3_TC0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), // IMX8_RST_HUB - GPIO 455
};
#define IMX8_RST_HUB IMX_GPIO_NR(4, 3)
#define USB_HC_SEL IMX_GPIO_NR(4, 6)
static void board_gpio_init(void)
{
int ret;
struct gpio_desc desc;
struct power_domain pd;
//imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
sc_pm_set_resource_power_mode( -1, SC_R_GPIO_4, SC_PM_PW_MODE_ON );
ret = dm_gpio_lookup_name("gpio4_3", &desc);
if (ret) {
printf("%s lookup GPIO@4_3 failed ret = %d\n", __func__, ret);
return;
}
ret = dm_gpio_request(&desc, "imx8_rst_hub");
if (ret) {
printf("%s request imx8_rst_hub failed ret = %d\n", __func__, ret);
return;
}
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
dm_gpio_set_value(&desc, 0);
ret = dm_gpio_lookup_name("gpio4_6", &desc);
if (ret) {
printf("%s lookup GPIO@4_6 failed ret = %d\n", __func__, ret);
return;
}
ret = dm_gpio_request(&desc, "usb_hc_sel");
if (ret) {
printf("%s request usb_hc_sel failed ret = %d\n", __func__, ret);
return;
}
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
dm_gpio_set_value(&desc, 0);
......@@ -229,13 +185,11 @@ static void board_gpio_init(void)
printf("%s lookup GPIO@4_20 failed ret = %d\n", __func__, ret);
return;
}
ret = dm_gpio_request(&desc, "bb_3v3_1");
if (ret) {
printf("%s request bb_3v3_1 failed ret = %d\n", __func__, ret);
return;
}
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
ret = dm_gpio_lookup_name("gpio4_24", &desc);
......@@ -243,13 +197,11 @@ static void board_gpio_init(void)
printf("%s lookup GPIO@4_24 failed ret = %d\n", __func__, ret);
return;
}
ret = dm_gpio_request(&desc, "bb_3v3_2");
if (ret) {
printf("%s request bb_3v3_2 failed ret = %d\n", __func__, ret);
return;
}
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
ret = dm_gpio_lookup_name("gpio4_23", &desc);
......@@ -257,13 +209,11 @@ static void board_gpio_init(void)
printf("%s lookup GPIO@4_23 failed ret = %d\n", __func__, ret);
return;
}
ret = dm_gpio_request(&desc, "bb_3v3_3");
if (ret) {
printf("%s request bb_3v3_3 failed ret = %d\n", __func__, ret);
return;
}
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
/* enable LVDS SAS boards */
......@@ -272,13 +222,11 @@ static void board_gpio_init(void)
printf("%s lookup GPIO1_6 failed ret = %d\n", __func__, ret);
return;
}
ret = dm_gpio_request(&desc, "lvds_enable");
if (ret) {
printf("%s request lvds_enable failed ret = %d\n", __func__, ret);
return;
}
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
/* enable MIPI SAS boards */
......@@ -287,190 +235,44 @@ static void board_gpio_init(void)
printf("%s lookup GPIO1_7 failed ret = %d\n", __func__, ret);
return;
}
ret = dm_gpio_request(&desc, "mipi_enable");
if (ret) {
printf("%s request mipi_enable failed ret = %d\n", __func__, ret);
return;
}
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
if (!power_domain_lookup_name("hsio_sata0", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("hsio_sata0 Power up failed! (error = %d)\n", ret);
}
if (!power_domain_lookup_name("hsio_pcie0", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("hsio_pcie0 Power up failed! (error = %d)\n", ret);
}
if (!power_domain_lookup_name("hsio_pcie1", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("hsio_pcie1 Power up failed! (error = %d)\n", ret);
}
if (!power_domain_lookup_name("hsio_gpio", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("hsio_gpio Power up failed! (error = %d)\n", ret);
}
lpcg_all_clock_on(HSIO_PCIE_X2_LPCG);
lpcg_all_clock_on(HSIO_PCIE_X1_LPCG);
lpcg_all_clock_on(HSIO_SATA_LPCG);
lpcg_all_clock_on(HSIO_PHY_X2_LPCG);
lpcg_all_clock_on(HSIO_PHY_X1_LPCG);
lpcg_all_clock_on(HSIO_PHY_X2_CRR0_LPCG);
lpcg_all_clock_on(HSIO_PHY_X1_CRR1_LPCG);
lpcg_all_clock_on(HSIO_PCIE_X2_CRR2_LPCG);
lpcg_all_clock_on(HSIO_PCIE_X1_CRR3_LPCG);
lpcg_all_clock_on(HSIO_SATA_CRR4_LPCG);
lpcg_all_clock_on(HSIO_MISC_LPCG);
lpcg_all_clock_on(HSIO_GPIO_LPCG);
imx8_iomux_setup_multiple_pads(board_pcie_pins, ARRAY_SIZE(board_pcie_pins));
}
#ifdef CONFIG_USB
// #ifdef CONFIG_USB_TCPC
// struct gpio_desc type_sel_desc;
// static iomux_cfg_t ss_mux_gpio[] = {
// SC_P_USB_SS3_TC3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
// SC_P_QSPI1A_SS0_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
// };
// struct tcpc_port port;
// struct tcpc_port_config port_config = {
// .i2c_bus = 0,
// .addr = 0x51,
// .port_type = TYPEC_PORT_DFP,
// };
// void ss_mux_select(enum typec_cc_polarity pol)
// {
// if (pol == TYPEC_POLARITY_CC1)
// dm_gpio_set_value(&type_sel_desc, 0);
// else
// dm_gpio_set_value(&type_sel_desc, 1);
// }
// static void setup_typec(void)
// {
// int ret;
// struct gpio_desc typec_en_desc;
// imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
// ret = dm_gpio_lookup_name("GPIO4_6", &type_sel_desc);
// if (ret) {
// printf("%s lookup GPIO4_6 failed ret = %d\n", __func__, ret);
// return;
// }
// ret = dm_gpio_request(&type_sel_desc, "typec_sel");
// if (ret) {
// printf("%s request typec_sel failed ret = %d\n", __func__, ret);
// return;
// }
// dm_gpio_set_dir_flags(&type_sel_desc, GPIOD_IS_OUT);
// ret = dm_gpio_lookup_name("GPIO4_19", &typec_en_desc);
// if (ret) {
// printf("%s lookup GPIO4_19 failed ret = %d\n", __func__, ret);
// return;
// }
// ret = dm_gpio_request(&typec_en_desc, "typec_en");
// if (ret) {
// printf("%s request typec_en failed ret = %d\n", __func__, ret);
// return;
// }
// /* Enable SS MUX */
// dm_gpio_set_dir_flags(&typec_en_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
// tcpc_init(&port, port_config, &ss_mux_select);
// }
// #endif
/*int board_usb_init(int index, enum usb_init_type init)
{
int ret = 0;
if (index == 1) {
if (init == USB_INIT_HOST) {
#ifdef CONFIG_USB_TCPC
ret = tcpc_setup_dfp_mode(&port);
#endif
#ifdef CONFIG_USB_CDNS3_GADGET
} else {
#ifdef CONFIG_USB_TCPC
ret = tcpc_setup_ufp_mode(&port);
printf("%d setufp mode %d\n", index, ret);
#endif
#endif
}
}
return ret;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
int ret = 0;
if (index == 1) {
if (init == USB_INIT_HOST) {
#ifdef CONFIG_USB_TCPC
ret = tcpc_disable_src_vbus(&port);
#endif
}
}
return ret;
}*/
/*
INIT
We just want one USB, HSIC, which is tested as second port.
As a consequence:
- the first call to board_usb_init must fail to speed up boot (but it could work, if needed)
- the second call to board_usb_init moves HUB RESET
For this, we cannot use index, as this is incremented only for
correctly initialized ports, so we use a different counter.
INIT
We just want one USB, HSIC, which is tested as second port.
As a consequence:
- the first call to board_usb_init must fail to speed up boot (but it could work, if needed) [???]
- the second call to board_usb_init moves HUB RESET
For this, we cannot use index, as this is incremented only for
correctly initialized ports, so we use a different counter.
Note that this order is independent on the presence of JP3, which only influences USB0 initialization result.
Note that this order is independent on the presence of JP3, which only influences USB0 initialization result.
CLEANUP
Instead, board_usb_cleanup is called just once, for the initialized port, so
there we reset to zero the local counter and move HUB RESET.
CLEANUP
Instead, board_usb_cleanup is called just once, for the initialized port, so
there we reset to zero the local counter and move HUB RESET.
*/
int board_usb_init(int index, enum usb_init_type init)
{
int ret;
struct gpio_desc desc;
sc_pm_set_resource_power_mode( -1, SC_R_GPIO_4, SC_PM_PW_MODE_ON );
dm_gpio_lookup_name("gpio4_3", &desc);
dm_gpio_lookup_name("gpio4_3", &desc);
dm_gpio_request(&desc, "imx8_rst_hub");
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
dm_gpio_set_value(&desc,1);
mdelay(100);
mdelay(100);
return 0;
}
......@@ -479,26 +281,21 @@ int board_usb_cleanup(int index, enum usb_init_type init)
{
int ret;
struct gpio_desc desc;
/* RESET just once */
sc_pm_set_resource_power_mode( -1, SC_R_GPIO_4, SC_PM_PW_MODE_ON );
/* RESET just once */
sc_pm_set_resource_power_mode( -1, SC_R_GPIO_4, SC_PM_PW_MODE_ON );
dm_gpio_lookup_name("gpio4_3", &desc);
dm_gpio_lookup_name("gpio4_3", &desc);
dm_gpio_request(&desc, "imx8_rst_hub");
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
dm_gpio_set_value(&desc,0);
return 0;
}
#endif
/* __________________________________________________________________________
* |__________________________________________________________________________|
*/
int checkboard( void ) {
print_bootinfo();
......@@ -528,6 +325,8 @@ int board_init( void ) {
return 0;
}
extern uint32_t _end_ofs;
int board_late_init(void)
{
char *fdt_file;
......@@ -551,53 +350,37 @@ int board_late_init(void)
env_set("sec_boot", "yes");
#endif
fdt_file = env_get("fdt_file");
if (fdt_file && !strcmp(fdt_file, "undefined")) {
#if defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY)
env_set("fdt_file", "imx8qm-mek-cockpit-ca53.dtb");
#elif defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY)
env_set("fdt_file", "imx8qm-mek-cockpit-ca72.dtb");
#else
m4_booted = m4_parts_booted();
if (m4_booted)
env_set("fdt_file", "imx8qm-mek-rpmsg.dtb");
else
env_set("fdt_file", "imx8qm-mek.dtb");
#endif
}
/* seco_config variables */
#ifdef CONFIG_SECO_ENV_MANAGER
gd->bsp_sources.kern_dev_list = &kern_dev_imx8_list[0];
gd->bsp_sources.kern_dev_num = kern_dev_imx8_size;
gd->bsp_sources.fdt_dev_list = &fdt_dev_imx8_list[0];
gd->bsp_sources.fdt_dev_num = fdt_dev_imx8_size;
gd->bsp_sources.fw_dev_list = firmware_dev_imx8_list;
gd->bsp_sources.fw_dev_num = firmware_dev_imx8_size;
gd->bsp_sources.kern_dev_list = &kern_dev_imx8_list[0];
gd->bsp_sources.kern_dev_num = kern_dev_imx8_size;
gd->bsp_sources.fdt_dev_list = &fdt_dev_imx8_list[0];
gd->bsp_sources.fdt_dev_num = fdt_dev_imx8_size;
gd->bsp_sources.fw_dev_list = firmware_dev_imx8_list;
gd->bsp_sources.fw_dev_num = firmware_dev_imx8_size;
#ifdef CONFIG_OF_LIBFDT_OVERLAY
gd->bsp_sources.fdt_overlay_dev_list = fdt_overlay_dev_imx8_list;
gd->bsp_sources.fdt_overlay_dev_num = fdt_overlay_dev_imx8_size;
gd->bsp_sources.fdt_overlay_dev_list = fdt_overlay_dev_imx8_list;
gd->bsp_sources.fdt_overlay_dev_num = fdt_overlay_dev_imx8_size;
#endif
gd->bsp_sources.ramfs_dev_list = &ramfs_dev_imx8_list[0];
gd->bsp_sources.ramfs_dev_num = ramfs_dev_imx8_size;
gd->bsp_sources.filesystem_dev_list = &filesystem_dev_imx8_list[0];
gd->bsp_sources.filesystem_dev_num = filesystem_dev_imx8_size;
gd->bsp_sources.ramfs_dev_list = &ramfs_dev_imx8_list[0];
gd->bsp_sources.ramfs_dev_num = ramfs_dev_imx8_size;
gd->bsp_sources.filesystem_dev_list = &filesystem_dev_imx8_list[0];
gd->bsp_sources.filesystem_dev_num = filesystem_dev_imx8_size;
#ifdef CONFIG_OF_LIBFDT_OVERLAY
if ( (VIDEO_STRAPS)c26_strap_conf->video == VIDEO_CFC_A1 ) {
gd->boot_setup.video_mode_list = video_mode_list_cfg_a1;
gd->boot_setup.video_mode_num = video_mode_size_cfg_a1;
} else if ( (VIDEO_STRAPS)c26_strap_conf->video == VIDEO_CFC_A2 ) {
gd->boot_setup.video_mode_list = video_mode_list_cfg_a2;
gd->boot_setup.video_mode_num = video_mode_size_cfg_a2;
} else {
gd->boot_setup.video_mode_list = NULL;
gd->boot_setup.video_mode_num = 0;
}
gd->boot_setup.overlay_peripheral_list = overlay_peripheral_list;
gd->boot_setup.overlay_peripheral_num = overlay_peripheral_size;
if ( (VIDEO_STRAPS)c26_strap_conf->video == VIDEO_CFC_A1 ) {
gd->boot_setup.video_mode_list = video_mode_list_a1;
gd->boot_setup.video_mode_num = video_mode_size_a1;
} else if ( (VIDEO_STRAPS)c26_strap_conf->video == VIDEO_CFC_A2 ) {
gd->boot_setup.video_mode_list = video_mode_list_a2;
gd->boot_setup.video_mode_num = video_mode_size_a2;
} else {
gd->boot_setup.video_mode_list = NULL;
gd->boot_setup.video_mode_num = 0;
}
gd->boot_setup.overlay_peripheral_list = overlay_peripheral_list;
gd->boot_setup.overlay_peripheral_num = overlay_peripheral_size;
#endif
#endif
......@@ -630,9 +413,6 @@ int board_late_init(void)
}
void board_quiesce_devices(void)
{
const char *power_on_devices[] = {
......@@ -663,6 +443,7 @@ void reset_cpu(ulong addr)
while(1);
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
......@@ -670,26 +451,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
}
#endif
// int board_mmc_get_env_dev(int devno)
// {
// /* Use EMMC */
// if (IS_ENABLED(CONFIG_XEN))
// return 0;
// return devno;
// }
// int mmc_map_to_kernel_blk(int dev_no)
// {
// /* Use EMMC */
// if (IS_ENABLED(CONFIG_XEN))
// return 0;
// return dev_no;
// }
extern uint32_t _end_ofs;
#ifdef CONFIG_ANDROID_SUPPORT
bool is_power_key_pressed(void) {
......
board/seco/imx8qm_c26/imx8qm_c26.h
+ 9
− 0
View file @ fbf36d6c
......@@ -8,6 +8,7 @@
#define _BOARD_MX8QM_SECO_C26_H__
#include "../common/muxing_mx8.h"
#define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT))
/* __________________________________________________________________________
* | |
......@@ -18,8 +19,16 @@ static iomux_cfg_t uart0_pads[] = {
SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
/* __________________________________________________________________________
* | |
* | PCIE |
* |__________________________________________________________________________|
*/
static iomux_cfg_t board_pcie_pins[] = {
SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
};
#endif /* _BOARD_MX8QM_SECO_C26_H__ */
\ No newline at end of file
board/seco/imx8qm_c43/MAINTAINERS
+ 1
− 2
View file @ fbf36d6c
TARGET_SECO_IMX8QM_C43
M: Stefano Radaelli <stefano.radaelli@seco.com>
M: Gianfranco Mariotti <gianfranco.mariotti@seco.com>
S: Maintained
F: board/seco/imx8qm_c43/env_conf.h
F: board/seco/imx8qm_c43/imx8qm_c43.c
......@@ -8,7 +8,6 @@ F: board/seco/imx8qm_c43/imximage.cfg
F: board/seco/imx8qm_c43/Kconfig
F: board/seco/imx8qm_c43/MAINTAINERS
F: board/seco/imx8qm_c43/Makefile
F: board/seco/imx8qm_c43/README
F: board/seco/imx8qm_c43/spl.c
F: board/seco/imx8qm_c43/strap_cfg.c
F: board/seco/imx8qm_c43/strap_cfg.h
......
board/seco/imx8qm_c43/env_conf.h
+ 2
− 2
View file @ fbf36d6c
......@@ -83,7 +83,7 @@ size_t filesystem_dev_imx8_size = sizeof( filesystem_dev_imx8_list ) / sizeof( f
video_mode_t video_mode_list_cfg_a1 [] = {
video_mode_t video_mode_list [] = {
{
/* NO DISPLAY */
.label = SECO_VIDEO_LABEL_NONE,
......@@ -262,7 +262,7 @@ video_mode_t video_mode_list_cfg_a1 [] = {
};
size_t video_mode_size_cfg_a1 = sizeof( video_mode_list_cfg_a1 ) / sizeof( video_mode_list_cfg_a1[0] );
size_t video_mode_size = sizeof( video_mode_list ) / sizeof( video_mode_list[0] );
......
board/seco/imx8qm_c43/imx8qm_c43.c
+ 28
− 239
View file @ fbf36d6c
......@@ -22,13 +22,12 @@
#include <asm/arch/sys_proto.h>
#include "../common/tcpc.h"
#include "command.h"
#include "../common/proto_seco.h"
#include "seco/seco_env_gd.h"
#include "imx8qm_c43.h"
#include "strap_cfg.h"
#include "asm/arch-imx8/imx8qm_lpcg.h"
#include "asm/arch-imx8/lpcg.h"
#include "dt-bindings/soc/imx8_pd.h"
DECLARE_GLOBAL_DATA_PTR;
......@@ -41,14 +40,6 @@ DECLARE_GLOBAL_DATA_PTR;
#include "env_conf.h"
#endif
static iomux_cfg_t seco_code[] = {
SC_P_LVDS1_I2C0_SDA | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), //SECO REVISION CODE 2
SC_P_ESAI1_TX4_RX1 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(GPIO_PAD_CTRL), //SECO REVISION CODE 3
SC_P_ESAI1_TX5_RX0 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(GPIO_PAD_CTRL), //SECO REVISION CODE 4
SC_P_LVDS1_GPIO01 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), //SECO RAM CODE 0
SC_P_LVDS1_I2C0_SCL | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), //SECO RAM CODE 1
};
/* __________________________________________________________________________
* | |
......@@ -58,17 +49,15 @@ static iomux_cfg_t seco_code[] = {
static void setup_iomux_uart( void ) {
imx8_iomux_setup_multiple_pads( uart0_pads, ARRAY_SIZE( uart0_pads ) );
}
/* __________________________________________________________________________
* | |
* | SECO CODE |
* | SECO CODE |
* |__________________________________________________________________________|
*/
static void setup_seco_code( void ) {
imx8_iomux_setup_multiple_pads( seco_code, ARRAY_SIZE( seco_code ) );
}
/* __________________________________________________________________________
* |__________________________________________________________________________|
*/
/* __________________________________________________________________________
* | |
......@@ -77,15 +66,15 @@ static void setup_seco_code( void ) {
*/
#define BOOT_VALIDATE IMX_GPIO_NR(2,31)
static void send_boot_validate( void ) {
boot_validate (BOOT_VALIDATE, SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL));
}
/* __________________________________________________________________________
* | |
* | DRAM |
* |__________________________________________________________________________|
*/
#define PHYS_DRAM_IS_1GB 0x40000000
#define PHYS_DRAM_IS_2GB 0x80000000
#define PHYS_DRAM_IS_3GB 0xc0000000
......@@ -130,8 +119,6 @@ void board_mem_get_layout(u64 *phys_sdram_1_start,
*phys_sdram_2_size = sdram_size;
}
/* __________________________________________________________________________
* | |
* | BOOT DEVICE |
......@@ -143,11 +130,10 @@ boot_mem_dev_t boot_mem_dev_list[SECO_NUM_BOOT_DEV] = {
};
int usdhc_devno[4] = { BOARD_BOOT_ID_EMMC, BOARD_BOOT_ID_SD, -1, -1};
/* __________________________________________________________________________
* |__________________________________________________________________________|
*/
int board_early_init_f(void)
{
sc_pm_clock_rate_t rate = SC_80MHZ;
......@@ -179,171 +165,7 @@ int board_early_init_f(void)
}
#define IMX8_RST_HUB IMX_GPIO_NR(4, 3)
#define USB_HC_SEL IMX_GPIO_NR(4, 6)
#define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT))
static iomux_cfg_t board_pcie_pins[] = {
SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
};
/*static iomux_cfg_t board_gpios[] = {
SC_P_USB_SS3_TC0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), // IMX8_RST_HUB - GPIO 455
SC_P_ENET1_MDC | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), // ETH_RST# - GPIO 370
};*/
static void board_gpio_init(void)
{
int ret;
//struct gpio_desc desc;
struct power_domain pd;
/*sc_pm_set_resource_power_mode( -1, SC_R_GPIO_1, SC_PM_PW_MODE_ON );
sc_pm_set_resource_power_mode( -1, SC_R_GPIO_4, SC_PM_PW_MODE_ON );*/
/*ret = dm_gpio_lookup_name("gpio4_24", &desc);
if (ret) {
printf("%s lookup GPIO@4_24 failed ret = %d\n", __func__, ret);
return;
}
ret = dm_gpio_request(&desc, "bb_3v3_2");
if (ret) {
printf("%s request bb_3v3_2 failed ret = %d\n", __func__, ret);
return;
}
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
ret = dm_gpio_lookup_name("gpio4_23", &desc);
if (ret) {
printf("%s lookup GPIO@4_23 failed ret = %d\n", __func__, ret);
return;
}
ret = dm_gpio_request(&desc, "bb_3v3_3");
if (ret) {
printf("%s request bb_3v3_3 failed ret = %d\n", __func__, ret);
return;
}
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);*/
if (!power_domain_lookup_name("hsio_sata0", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("hsio_sata0 Power up failed! (error = %d)\n", ret);
}
if (!power_domain_lookup_name("hsio_pcie0", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("hsio_pcie0 Power up failed! (error = %d)\n", ret);
}
if (!power_domain_lookup_name("hsio_pcie1", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("hsio_pcie1 Power up failed! (error = %d)\n", ret);
}
if (!power_domain_lookup_name("hsio_gpio", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("hsio_gpio Power up failed! (error = %d)\n", ret);
}
lpcg_all_clock_on(HSIO_PCIE_X2_LPCG);
lpcg_all_clock_on(HSIO_PCIE_X1_LPCG);
lpcg_all_clock_on(HSIO_SATA_LPCG);
lpcg_all_clock_on(HSIO_PHY_X2_LPCG);
lpcg_all_clock_on(HSIO_PHY_X1_LPCG);
lpcg_all_clock_on(HSIO_PHY_X2_CRR0_LPCG);
lpcg_all_clock_on(HSIO_PHY_X1_CRR1_LPCG);
lpcg_all_clock_on(HSIO_PCIE_X2_CRR2_LPCG);
lpcg_all_clock_on(HSIO_PCIE_X1_CRR3_LPCG);
lpcg_all_clock_on(HSIO_SATA_CRR4_LPCG);
lpcg_all_clock_on(HSIO_MISC_LPCG);
lpcg_all_clock_on(HSIO_GPIO_LPCG);
imx8_iomux_setup_multiple_pads(board_pcie_pins, ARRAY_SIZE(board_pcie_pins));
}
#ifdef CONFIG_USB
// #ifdef CONFIG_USB_TCPC
// struct gpio_desc type_sel_desc;
// static iomux_cfg_t ss_mux_gpio[] = {
// SC_P_USB_SS3_TC3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
// SC_P_QSPI1A_SS0_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
// };
// struct tcpc_port port;
// struct tcpc_port_config port_config = {
// .i2c_bus = 0,
// .addr = 0x51,
// .port_type = TYPEC_PORT_DFP,
// };
// void ss_mux_select(enum typec_cc_polarity pol)
// {
// if (pol == TYPEC_POLARITY_CC1)
// dm_gpio_set_value(&type_sel_desc, 0);
// else
// dm_gpio_set_value(&type_sel_desc, 1);
// }
// static void setup_typec(void)
// {
// int ret;
// struct gpio_desc typec_en_desc;
// imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
// ret = dm_gpio_lookup_name("GPIO4_6", &type_sel_desc);
// if (ret) {
// printf("%s lookup GPIO4_6 failed ret = %d\n", __func__, ret);
// return;
// }
// ret = dm_gpio_request(&type_sel_desc, "typec_sel");
// if (ret) {
// printf("%s request typec_sel failed ret = %d\n", __func__, ret);
// return;
// }
// dm_gpio_set_dir_flags(&type_sel_desc, GPIOD_IS_OUT);
// ret = dm_gpio_lookup_name("GPIO4_19", &typec_en_desc);
// if (ret) {
// printf("%s lookup GPIO4_19 failed ret = %d\n", __func__, ret);
// return;
// }
// ret = dm_gpio_request(&typec_en_desc, "typec_en");
// if (ret) {
// printf("%s request typec_en failed ret = %d\n", __func__, ret);
// return;
// }
// /* Enable SS MUX */
// dm_gpio_set_dir_flags(&typec_en_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
// tcpc_init(&port, port_config, &ss_mux_select);
// }
// #endif
int board_usb_init(int index, enum usb_init_type init)
{
int ret = 0;
......@@ -386,7 +208,6 @@ int board_usb_cleanup(int index, enum usb_init_type init)
/* __________________________________________________________________________
* |__________________________________________________________________________|
*/
int checkboard( void ) {
print_bootinfo();
......@@ -400,9 +221,7 @@ int checkboard( void ) {
int board_init( void ) {
if (IS_ENABLED(CONFIG_XEN))
return 0;
board_gpio_init();
#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
{
int ret = snvs_security_sc_init();
......@@ -416,14 +235,12 @@ int board_init( void ) {
return 0;
}
extern uint32_t _end_ofs;
int board_late_init(void)
{
char *fdt_file;
/*#if defined(CONFIG_SECO_ENV_MANAGER) && defined(CONFIG_OF_LIBFDT_OVERLAY)
strap_conf_t *c43_strap_conf = (strap_conf_t *)gd->strap_configuration;
#endif*/
build_info();
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
......@@ -436,35 +253,29 @@ int board_late_init(void)
env_set("sec_boot", "yes");
#endif
fdt_file = env_get("fdt_file");
if (fdt_file && !strcmp(fdt_file, "undefined")) {
env_set("fdt_file", "seco-imx8qm-c43.dtb");
}
/* seco_config variables */
#ifdef CONFIG_SECO_ENV_MANAGER
gd->bsp_sources.kern_dev_list = &kern_dev_imx8_list[0];
gd->bsp_sources.kern_dev_num = kern_dev_imx8_size;
gd->bsp_sources.fdt_dev_list = &fdt_dev_imx8_list[0];
gd->bsp_sources.fdt_dev_num = fdt_dev_imx8_size;
gd->bsp_sources.fw_dev_list = firmware_dev_imx8_list;
gd->bsp_sources.fw_dev_num = firmware_dev_imx8_size;
gd->bsp_sources.kern_dev_list = &kern_dev_imx8_list[0];
gd->bsp_sources.kern_dev_num = kern_dev_imx8_size;
gd->bsp_sources.fdt_dev_list = &fdt_dev_imx8_list[0];
gd->bsp_sources.fdt_dev_num = fdt_dev_imx8_size;
gd->bsp_sources.fw_dev_list = firmware_dev_imx8_list;
gd->bsp_sources.fw_dev_num = firmware_dev_imx8_size;
#ifdef CONFIG_OF_LIBFDT_OVERLAY
gd->bsp_sources.fdt_overlay_dev_list = fdt_overlay_dev_imx8_list;
gd->bsp_sources.fdt_overlay_dev_num = fdt_overlay_dev_imx8_size;
gd->bsp_sources.fdt_overlay_dev_list = fdt_overlay_dev_imx8_list;
gd->bsp_sources.fdt_overlay_dev_num = fdt_overlay_dev_imx8_size;
#endif
gd->bsp_sources.ramfs_dev_list = &ramfs_dev_imx8_list[0];
gd->bsp_sources.ramfs_dev_num = ramfs_dev_imx8_size;
gd->bsp_sources.filesystem_dev_list = &filesystem_dev_imx8_list[0];
gd->bsp_sources.filesystem_dev_num = filesystem_dev_imx8_size;
gd->bsp_sources.ramfs_dev_list = &ramfs_dev_imx8_list[0];
gd->bsp_sources.ramfs_dev_num = ramfs_dev_imx8_size;
gd->bsp_sources.filesystem_dev_list = &filesystem_dev_imx8_list[0];
gd->bsp_sources.filesystem_dev_num = filesystem_dev_imx8_size;
#ifdef CONFIG_OF_LIBFDT_OVERLAY
gd->boot_setup.video_mode_list = video_mode_list_cfg_a1;
gd->boot_setup.video_mode_num = video_mode_size_cfg_a1;
gd->boot_setup.video_mode_list = video_mode_list;
gd->boot_setup.video_mode_num = video_mode_size;
gd->boot_setup.overlay_peripheral_list = overlay_peripheral_list;
gd->boot_setup.overlay_peripheral_num = overlay_peripheral_size;
gd->boot_setup.overlay_peripheral_list = overlay_peripheral_list;
gd->boot_setup.overlay_peripheral_num = overlay_peripheral_size;
#endif
#endif
......@@ -497,9 +308,6 @@ int board_late_init(void)
}
void board_quiesce_devices(void)
{
const char *power_on_devices[] = {
......@@ -530,6 +338,7 @@ void reset_cpu(ulong addr)
while(1);
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
......@@ -537,26 +346,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
}
#endif
// int board_mmc_get_env_dev(int devno)
// {
// /* Use EMMC */
// if (IS_ENABLED(CONFIG_XEN))
// return 0;
// return devno;
// }
// int mmc_map_to_kernel_blk(int dev_no)
// {
// /* Use EMMC */
// if (IS_ENABLED(CONFIG_XEN))
// return 0;
// return dev_no;
// }
extern uint32_t _end_ofs;
#ifdef CONFIG_ANDROID_SUPPORT
bool is_power_key_pressed(void) {
......
board/seco/imx8qm_c43/imx8qm_c43.h
+ 22
− 0
View file @ fbf36d6c
......@@ -8,6 +8,7 @@
#define _BOARD_MX8QM_SECO_C43_H__
#include "../common/muxing_mx8.h"
#define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT))
/* __________________________________________________________________________
* | |
......@@ -18,8 +19,29 @@ static iomux_cfg_t uart0_pads[] = {
SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
/* __________________________________________________________________________
* | |
* | SECO CODE |
* |__________________________________________________________________________|
*/
static iomux_cfg_t seco_code[] = {
SC_P_LVDS1_I2C0_SDA | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), //SECO REVISION CODE 2
SC_P_ESAI1_TX4_RX1 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(GPIO_PAD_CTRL), //SECO REVISION CODE 3
SC_P_ESAI1_TX5_RX0 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(GPIO_PAD_CTRL), //SECO REVISION CODE 4
SC_P_LVDS1_GPIO01 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), //SECO RAM CODE 0
SC_P_LVDS1_I2C0_SCL | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), //SECO RAM CODE 1
};
/* __________________________________________________________________________
* | |
* | PCIE |
* |__________________________________________________________________________|
*/
static iomux_cfg_t board_pcie_pins[] = {
SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
};
#endif /* _BOARD_MX8QM_SECO_C43_H__ */
\ No newline at end of file
configs/seco_imx8qm_c26_defconfig
+ 1
− 1
View file @ fbf36d6c
......@@ -78,7 +78,7 @@ CONFIG_SDP_LOADADDR=0x80400000
# FDT
CONFIG_DEFAULT_DEVICE_TREE="seco-imx8qm-c26"
CONFIG_DEFAULT_FDT_FILE="seco-imx8qm-c26"
CONFIG_DEFAULT_FDT_FILE="seco-imx8qm-c26.dtb"
CONFIG_OF_LIST="seco-imx8qm-c26"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_OF_LIBFDT=y
......
configs/seco_imx8qm_c43_defconfig
+ 1
− 1
View file @ fbf36d6c
......@@ -78,7 +78,7 @@ CONFIG_SDP_LOADADDR=0x80400000
# FDT
CONFIG_DEFAULT_DEVICE_TREE="seco-imx8qm-c43"
CONFIG_DEFAULT_FDT_FILE="seco-imx8qm-c43"
CONFIG_DEFAULT_FDT_FILE="seco-imx8qm-c43.dtb"
CONFIG_OF_LIST="seco-imx8qm-c43"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_OF_LIBFDT=y
......
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