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Commit a6adb321 authored by Yuri Mazzuoli's avatar Yuri Mazzuoli
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[962] fix qd 4x512M ram configuration not booting

parent f97a2135
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...@@ -44,7 +44,7 @@ __maybe_unused static int mx6dl_4x512_dcd_table[] = { ...@@ -44,7 +44,7 @@ __maybe_unused static int mx6dl_4x512_dcd_table[] = {
0x021b001c, 0x00008000, // MX6_MMDC_P0_MDSCR 0x021b001c, 0x00008000, // MX6_MMDC_P0_MDSCR
0x021b002c, 0x000026D2, // MX6_MMDC_P0_MDRWD 0x021b002c, 0x000026D2, // MX6_MMDC_P0_MDRWD
0x021b0030, 0x006B1023, // MX6_MMDC_P0_MDOR 0x021b0030, 0x006B1023, // MX6_MMDC_P0_MDOR
/* CS0_END = 1024MB (1024 + 256) in step da 256Mb -> [(1280*8/256) - 1] */ /* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */
0x021b0040, 0x00000047, // MX6_MMDC_P0_MDASP 0x021b0040, 0x00000047, // MX6_MMDC_P0_MDASP
/* SDE_1=0; ROW=3; BL=1; DSIZ=1 -> 32 bit */ /* SDE_1=0; ROW=3; BL=1; DSIZ=1 -> 32 bit */
0x021b0000, 0x841A0000, // MX6_MMDC_P0_MDCTL 0x021b0000, 0x841A0000, // MX6_MMDC_P0_MDCTL
...@@ -67,48 +67,48 @@ __maybe_unused static int mx6dl_4x512_dcd_table[] = { ...@@ -67,48 +67,48 @@ __maybe_unused static int mx6dl_4x512_dcd_table[] = {
__maybe_unused static int mx6qd_4x512_dcd_table[] = { __maybe_unused static int mx6qd_4x512_dcd_table[] = {
/* Write Leveling */ /* Write Leveling */
0x021b080c, 0x001F001F, // MX6_MMDC_P0_MPWLDECTRL0 0x021b080c, 0x001F001F, // MX6_MMDC_P0_MPWLDECTRL0
0x021b0810, 0x001F001F, // MX6_MMDC_P0_MPWLDECTRL1 0x021b0810, 0x001F001F, // MX6_MMDC_P0_MPWLDECTRL1
0x021b480c, 0x001F0001, // MX6_MMDC_P1_MPWLDECTRL0 0x021b480c, 0x001F001F, // MX6_MMDC_P1_MPWLDECTRL0
0x021b4810, 0x001F001F, // MX6_MMDC_P1_MPWLDECTRL1 0x021b4810, 0x001F001F, // MX6_MMDC_P1_MPWLDECTRL1
/* DQS gating, read delay, write delay calibration values */ /* DQS gating, read delay, write delay calibration values */
0x021b083c, 0x431A0326, // MX6_MMDC_P0_MPDGCTRL0 0x021b083c, 0x432C0332, // MX6_MMDC_P0_MPDGCTRL0
0x021b0840, 0x0323031B, // MX6_MMDC_P0_MPDGCTRL1 0x021b0840, 0x03380335, // MX6_MMDC_P0_MPDGCTRL1
0x021b483c, 0x433F0340, // MX6_MMDC_P1_MPDGCTRL0 0x021b483c, 0x433A0342, // MX6_MMDC_P1_MPDGCTRL0
0x021b4840, 0x0345031C, // MX6_MMDC_P1_MPDGCTRL1 0x021b4840, 0x033F0323, // MX6_MMDC_P1_MPDGCTRL1
/* Read calibration */ /* Read calibration */
0x021b0848, 0x40343137, // MX6_MMDC_P0_MPRDDLCTL 0x021b0848, 0x48414146, // MX6_MMDC_P0_MPRDDLCTL
0x021b4848, 0x40372F45, // MX6_MMDC_P1_MPRDDLCTL 0x021b4848, 0x40403648, // MX6_MMDC_P1_MPRDDLCTL
/* write calibrttion */ /* write calibrttion */
0x021b0850, 0x32414741, // MX6_MMDC_P0_MPWRDLCTL 0x021b0850, 0x40424744, // MX6_MMDC_P0_MPWRDLCTL
0x021b4850, 0x4731473C, // MX6_MMDC_P1_MPWRDLCTL 0x021b4850, 0x463F4A3D, // MX6_MMDC_P1_MPWRDLCTL
/* Complete calibration by forced measurement */ /* Complete calibration by forced measurement */
0x021b08b8, 0x00000800, // MX6_MMDC_P0_MPMUR0 0x021b08b8, 0x00000800, // MX6_MMDC_P0_MPMUR0
0x021b48b8, 0x00000800, // MX6_MMDC_P1_MPMUR0 0x021b48b8, 0x00000800, // MX6_MMDC_P1_MPMUR0
/* ========== MMDC init ========== */ /* ========== MMDC init ========== */
/* in DDR3, 64-bit mode, only MMDC0 is init */ /* in DDR3, 64-bit mode, only MMDC0 is init */
0x021b0004, 0x00020036, // MX6_MMDC_P0_MDPDC 0x021b0004, 0x00020036, // MX6_MMDC_P0_MDPDC
0x021b0008, 0x09444040, // MX6_MMDC_P0_MDOTC 0x021b0008, 0x09444040, // MX6_MMDC_P0_MDOTC
0x021b000c, 0x898E7955, // MX6_MMDC_P0_MDCFG0 0x021b000c, 0x898E7955, // MX6_MMDC_P0_MDCFG0
0x021b0010, 0xFF328F64, // MX6_MMDC_P0_MDCFG1 0x021b0010, 0xFF328F64, // MX6_MMDC_P0_MDCFG1
0x021b0014, 0x01FF00DB, // MX6_MMDC_P0_MDCFG2 0x021b0014, 0x01FF00DB, // MX6_MMDC_P0_MDCFG2
0x021b0018, 0x00001740, // MX6_MMDC_P0_MDMISC 0x021b0018, 0x00011740, // MX6_MMDC_P0_MDMISC
0x021b001c, 0x00008000, // MX6_MMDC_P0_MDSCR 0x021b001c, 0x00008000, // MX6_MMDC_P0_MDSCR
0x021b002c, 0x000026D2, // MX6_MMDC_P0_MDRWD 0x021b002c, 0x000026D2, // MX6_MMDC_P0_MDRWD
0x021b0030, 0x008E1023, // MX6_MMDC_P0_MDOR 0x021b0030, 0x008E1023, // MX6_MMDC_P0_MDOR
/* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */ /* CS0_END = 1024MB (1024 + 256) in step da 256Mb -> [(1280*8/256) - 1] */
0x021b0040, 0x00000047, // MX6_MMDC_P0_MDASP 0x021b0040, 0x00000047, // MX6_MMDC_P0_MDASP
/* SDE_1=0; ROW=4; BL=1; DSIZ=2 -> 64 bit */ /* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */
0x021b0000, 0x841A0000, // MX6_MMDC_P0_MDCTL 0x021b0000, 0x841A0000, // MX6_MMDC_P0_MDCTL
/* Initialize DDR3 on CS_0 */ /* Initialize DDR3 on CS_0 */
0x021b001c, 0x04008032, // MX6_MMDC_P0_MDSCR 0x021b001c, 0x02088032, // MX6_MMDC_P0_MDSCR
0x021b001c, 0x00008033, // MX6_MMDC_P0_MDSCR 0x021b001c, 0x00008033, // MX6_MMDC_P0_MDSCR
0x021b001c, 0x00048031, // MX6_MMDC_P0_MDSCR 0x021b001c, 0x00048031, // MX6_MMDC_P0_MDSCR
/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */ /* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */
0x021b001c, 0x09408030, // MX6_MMDC_P0_MDSCR 0x021b001c, 0x09408030, // MX6_MMDC_P0_MDSCR
/* ZQ - Calibration */ /* ZQ - Calibration */
0x021b0800, 0xa1390003, // MX6_MMDC_P0_MPZQHWCTRL 0x021b0800, 0xa1390003, // MX6_MMDC_P0_MDSCR
0x021b001c, 0x04008040, // MX6_MMDC_P0_MDSCR 0x021b001c, 0x04008040, // MX6_MMDC_P0_MDSCR
0x021b0020, 0x00007800, // MX6_MMDC_P0_MDREF 0x021b0020, 0x00007800, // MX6_MMDC_P0_MDREF
0x021b0818, 0x00022227, // MX6_MMDC_P0_MPODTCTRL 0x021b0818, 0x00022227, // MX6_MMDC_P0_MPODTCTRL
...@@ -119,6 +119,7 @@ __maybe_unused static int mx6qd_4x512_dcd_table[] = { ...@@ -119,6 +119,7 @@ __maybe_unused static int mx6qd_4x512_dcd_table[] = {
}; };
#endif /* CONFIG_SECOMX6_2GB_4x512 */ #endif /* CONFIG_SECOMX6_2GB_4x512 */
......
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