Skip to content
Snippets Groups Projects
Commit 46c8205b authored by Nicola Sparnacci's avatar Nicola Sparnacci
Browse files

[SANTINO][DDR] Add 1GB (2x512MB) DDR calibration

parent 60c61b7b
No related branches found
No related tags found
No related merge requests found
/*
* (C) Copyright 2015 Seco
*
* Author: Davide Cardillo <davide.cardillo@seco.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SECO_SBC_SANTINO_DDR_CONFIG_1GB_2x512_H_
#define _SECO_SBC_SANTINO_DDR_CONFIG_1GB_2x512_H_
#include "../common/ddr_conf.h"
#if defined( CONFIG_SECOMX6_1GB_2x512 )
__maybe_unused static int mx6solo_2x512_dcd_table[] = {
/* Write Leveling */
0x021b080c, 0x004C0057, // MX6_MMDC_P0_MPWLDECTRL0
0x021b0810, 0x00240028, // MX6_MMDC_P0_MPWLDECTRL1
/* DQS gating, read delay, write delay calibration values */
0x021b083c, 0x423C0238, // MX6_MMDC_P0_MPDGCTRL0
0x021b0840, 0x0214021C, // MX6_MMDC_P0_MPDGCTRL1
/* Read calibration */
0x021b0848, 0x42484A4A, // MX6_MMDC_P0_MPRDDLCTL
/* write calibrttion */
0x021b0850, 0x3C38322E, // MX6_MMDC_P0_MPWRDLCTL
/* Complete calibration by forced measurement */
0x021b08b8, 0x00000800, // MX6_MMDC_P0_MPMUR0
/* ========== MMDC init ========== */
/* in DDR3, 64-bit mode, only MMDC0 is init */
0x021b0004, 0x0002002D, // MX6_MMDC_P0_MDPDC
0x021b0008, 0x00333040, // MX6_MMDC_P0_MDOTC
0x021b000c, 0x676B52F3, // MX6_MMDC_P0_MDCFG0
0x021b0010, 0xB66E8B63, // MX6_MMDC_P0_MDCFG1
0x021b0014, 0x01FF00DB, // MX6_MMDC_P0_MDCFG2
0x021b0018, 0x00001740, // MX6_MMDC_P0_MDMISC
0x021b001c, 0x00008000, // MX6_MMDC_P0_MDSCR
0x021b002c, 0x000026d2, // MX6_MMDC_P0_MDRWD
0x021b0030, 0x006B1023, // MX6_MMDC_P0_MDOR
/* CS0_END = 1280MB (1024 + 256) in step da 256Mb -> [(768*8/256) - 1] */
0x021b0040, 0x00000027, // MX6_MMDC_P0_MDASP
/* SDE_1=0; ROW=3; BL=1; DSIZ=1 -> 32 bit */
0x021b0000, 0x83190000, // MX6_MMDC_P0_MDCTL
/* Initialize DDR3 on CS_0 */
0x021b001c, 0x04008032, // MX6_MMDC_P0_MDSCR
0x021b001c, 0x00008033, // MX6_MMDC_P0_MDSCR
0x021b001c, 0x00048031, // MX6_MMDC_P0_MDSCR
/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */
0x021b001c, 0x05208030, // MX6_MMDC_P0_MDSCR
/* ZQ - Calibration */
0x021b0800, 0xa1390003, // MX6_MMDC_P0_MPZQHWCTRL
0x021b001c, 0x04008040, // MX6_MMDC_P0_MDSCR
0x021b0020, 0x00007800, // MX6_MMDC_P0_MDREF
0x021b0818, 0x00022227, // MX6_MMDC_P0_MPODTCTRL
0x021b0004, 0x0002556D, // MX6_MMDC_P0_MDPDC
0x021b0404, 0x00011006, // MX6_MMDC_P0_MAPSR
0x021b001c, 0x00000000, // MX6_MMDC_P0_MDSCR
};
__maybe_unused static int mx6dl_2x512_dcd_table[] = {
/* Write Leveling */
0x021b080c, 0x004C0057, // MX6_MMDC_P0_MPWLDECTRL0
0x021b0810, 0x00240028, // MX6_MMDC_P0_MPWLDECTRL1
/* DQS gating, read delay, write delay calibration values */
0x021b083c, 0x423C0238, // MX6_MMDC_P0_MPDGCTRL0
0x021b0840, 0x0214021C, // MX6_MMDC_P0_MPDGCTRL1
/* Read calibration */
0x021b0848, 0x42484A4A, // MX6_MMDC_P0_MPRDDLCTL
/* write calibrttion */
0x021b0850, 0x3C38322E, // MX6_MMDC_P0_MPWRDLCTL
/* Complete calibration by forced measurement */
0x021b08b8, 0x00000800, // MX6_MMDC_P0_MPMUR0
/* ========== MMDC init ========== */
/* in DDR3, 64-bit mode, only MMDC0 is init */
0x021b0004, 0x0002002D, // MX6_MMDC_P0_MDPDC
0x021b0008, 0x00333040, // MX6_MMDC_P0_MDOTC
0x021b000c, 0x3F4352F3, // MX6_MMDC_P0_MDCFG0
0x021b0010, 0xB66E8B63, // MX6_MMDC_P0_MDCFG1
0x021b0014, 0x01FF00DB, // MX6_MMDC_P0_MDCFG2
0x021b0018, 0x00001740, // MX6_MMDC_P0_MDMISC
0x021b001c, 0x00008000, // MX6_MMDC_P0_MDSCR
0x021b002c, 0x000026D2, // MX6_MMDC_P0_MDRWD
0x021b0030, 0x00431023, // MX6_MMDC_P0_MDOR
/* CS0_END = 768MB (512 + 256) in step da 256Mb -> [(2304*8/256) - 1] */
0x021b0040, 0x00000017, // MX6_MMDC_P0_MDASP
/* SDE_1=0; ROW=3; BL=1; DSIZ=1 -> 32 bit */
0x021b0000, 0x83190000, // MX6_MMDC_P0_MDCTL
/* Initialize DDR3 on CS_0 */
0x021b001c, 0x02008032, // MX6_MMDC_P0_MDSCR
0x021b001c, 0x00008033, // MX6_MMDC_P0_MDSCR
0x021b001c, 0x00048031, // MX6_MMDC_P0_MDSCR
/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */
0x021b001c, 0x05208030, // MX6_MMDC_P0_MDSCR
/* ZQ - Calibration */
0x021b0800, 0xa1390003, // MX6_MMDC_P0_MPZQHWCTRL
0x021b001c, 0x04008040, // MX6_MMDC_P0_MDSCR
0x021b0020, 0x00007800, // MX6_MMDC_P0_MDREF
0x021b0818, 0x00022227, // MX6_MMDC_P0_MPODTCTRL
0x021b0004, 0x0002556D, // MX6_MMDC_P0_MDPDC
0x021b0404, 0x00011006, // MX6_MMDC_P0_MAPSR
0x021b001c, 0x00000000, // MX6_MMDC_P0_MDSCR
};
#endif /* CONFIG_SECOMX6_512MB_2x256 */
#endif /* _SECO_SBC_SANTINO_DDR_CONFIG_1GB_2x512_H_ */
......@@ -1679,16 +1679,16 @@ int spl_start_uboot(void)
// ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
// }
#include "ddr_config_2x256.h"
#include "ddr_config_2x512.h"
static void spl_dram_init( void ) {
#if defined( CONFIG_SECOMX6_512MB_2x256 )
// if ( is_mx6dl( ) ) {
ddr_init( mx6dl_32bit_dcd_table, ARRAY_SIZE( mx6dl_32bit_dcd_table ) );
ddr_init( mx6dl_2x256_dcd_table, ARRAY_SIZE( mx6dl_2x256_dcd_table ) );
// } else if ( is_mx6solo( ) ) {
// }
#elif defined( CONFIG_SECOMX6_1GB_2x512 )
ddr_init( mx6dl_64bit_dcd_table, ARRAY_SIZE( mx6dl_64bit_dcd_table ) );
ddr_init( mx6dl_2x512_dcd_table, ARRAY_SIZE( mx6dl_2x512_dcd_table ) );
#endif
}
......
......@@ -10,7 +10,7 @@ CONFIG_ENV_OFFSET=0xE0000
CONFIG_ENV_SIZE=0x2000
# RAM CONFIGURATION
CONFIG_SECOMX6_512MB_2x256=y
CONFIG_SECOMX6_1GB_2x512=y
# SPL
CONFIG_SPL=y
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment