[A75] fix eMMC reset and pad control at SPL

board/seco/imx6qdl_a75/imx6qdl_a75.c

@@ -95,6 +95,7 @@ boot_mem_dev_t boot_mem_dev_list[SECO_NUM_BOOT_DEV] = {
 #ifdef CONFIG_SPL_BUILD
 
 #define USDHC4_CD_GPIO	                          IMX_GPIO_NR(2, 6)
+#define USDHC3_RST_GPIO                           IMX_GPIO_NR(7, 8)
 
 
 /* USDHC map:
@@ -109,8 +110,8 @@ struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 
 
 struct usdhc_l usdhc_list_spl[CONFIG_SYS_FSL_USDHC_NUM] = {
-	{usdhc3_pads, ARRAY_SIZE(usdhc3_pads), -1, -1},
-	{usdhc4_pads, ARRAY_SIZE(usdhc4_pads), USDHC4_CD_GPIO, -1},
+	{usdhc3_pads, ARRAY_SIZE(usdhc3_pads)/2, -1, USDHC3_RST_GPIO},
+	{usdhc4_pads, ARRAY_SIZE(usdhc4_pads)/2, USDHC4_CD_GPIO, -1},
 };
 
 enum mxc_clock usdhc_clk[CONFIG_SYS_FSL_USDHC_NUM] = {
@@ -162,7 +163,8 @@ int board_mmc_init( struct bd_info *bis ) {
 
 	print_boot_device( );
 	
-	//SETUP_IOMUX_PADS( usdhc_list_spl[index].pad );	
+	imx_iomux_v3_setup_multiple_pads( usdhc_list_spl[index].pad,
+				usdhc_list_spl[index].num );
 	usdhc_cfg[index].sdhc_clk = mxc_get_clock( usdhc_clk[index] );
 	gd->arch.sdhc_clk = usdhc_cfg[index].sdhc_clk;
 	ret = fsl_esdhc_initialize( bis, &usdhc_cfg[index] );

board/seco/imx6qdl_a75/imx6qdl_a75.h

@@ -48,6 +48,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
 	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };