[D18] enable DP83867 ethernet ports

arch/arm64/boot/dts/seco/seco-imx8mp-d18.dts

@@ -7,6 +7,7 @@
 
 #include <dt-bindings/usb/pd.h>
 #include "include/imx8mp.dtsi"
+#include "dt-bindings/net/ti-dp83867.h"
 
 / {
 	model = "SECO i.MX8MPlus LPDDR4 D18 board";
@@ -129,6 +130,9 @@
 	pinctrl-0 = <&pinctrl_eqos>;
 	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy0>;
+	phy-reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
+	phy-reset-active-low;
+	phy-reset-duration = <1>;
 	status = "okay";
 
 	mdio {
@@ -137,11 +141,12 @@
 		#size-cells = <0>;
 
 		ethphy0: ethernet-phy@1 {
+			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
 			compatible = "ethernet-phy-ieee802.3-c22";
 			reg = <1>;
 			eee-broken-1000t;
-			rtl821x,aldps-disable;
-			rtl821x,clkout-disable;
 		};
 	};
 };
@@ -151,18 +156,21 @@
 	pinctrl-0 = <&pinctrl_fec>;
 	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy1>;
-	fsl,magic-packet;
+	phy-reset-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
+	phy-reset-active-low;
+	phy-reset-duration = <1>;
 	status = "okay";
 
 	mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		ethphy1: ethernet-phy@1 {
+		ethphy1: ethernet-phy@2 {
+			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
 			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <1>;
-			eee-broken-1000t;
-			rtl821x,clkout-disable;
+			reg = <2>;
 		};
 	};
 };
@@ -628,7 +636,7 @@
 			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f
 			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
 			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
-			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x19
+			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21		0x19
 		>;
 	};
 
@@ -648,7 +656,7 @@
 			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
 			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
 			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
-			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19
+			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20		0x19
 		>;
 	};
 
@@ -767,12 +775,6 @@
 		>;
 	};
 
-	pinctrl_typec_mux: typec1muxgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x16
-		>;
-	};
-
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49