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Commit d6c10080 authored by Gianfranco Mariotti's avatar Gianfranco Mariotti
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[i.MX8MP][DRIVER] LDB clock: free frequency assignment

The current LVDS driver implementation from the NXP kernel only supports
74.25 MHz single channel and 74.25/148.5 MHz dual channel LVDS.
If a different frequency is set, the value would default to one of those
frequencies: skip this clock constrain.
parent 109d184a
1 merge request!101[i.MX8MP][D18] Upgrade hardware support
......@@ -16,6 +16,8 @@
#include "imx-drm.h"
#define CONFIG_DRM_SECO_IMX8MP_LDB
#define DRIVER_NAME "imx8mp-ldb"
#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
......@@ -168,11 +170,13 @@ imx8mp_ldb_encoder_atomic_check(struct drm_encoder *encoder,
struct imx8mp_ldb_channel *imx8mp_ldb_ch =
enc_to_imx8mp_ldb_ch(encoder);
struct ldb_channel *ldb_ch = &imx8mp_ldb_ch->base;
struct drm_display_info *di = &conn_state->connector->display_info;
u32 bus_format = ldb_ch->bus_format;
#ifndef CONFIG_DRM_SECO_IMX8MP_LDB
struct imx8mp_ldb *imx8mp_ldb = imx8mp_ldb_ch->imx8mp_ldb;
struct ldb *ldb = &imx8mp_ldb->base;
struct drm_display_info *di = &conn_state->connector->display_info;
struct drm_display_mode *mode = &crtc_state->adjusted_mode;
u32 bus_format = ldb_ch->bus_format;
#endif
/* Bus format description in DT overrides connector display info. */
if (!bus_format && di->num_bus_formats) {
......@@ -194,6 +198,12 @@ imx8mp_ldb_encoder_atomic_check(struct drm_encoder *encoder,
return -EINVAL;
}
/*
* This forces panel clock to:
* - 148.5MHz or 74.25MHz for Dual Channel
* - 74.25MHz for Single Channel
*/
#ifndef CONFIG_DRM_SECO_IMX8MP_LDB
/*
* Due to limited video PLL frequency points on i.MX8mp,
* we do mode fixup here in case any mode is unsupported.
......@@ -202,6 +212,7 @@ imx8mp_ldb_encoder_atomic_check(struct drm_encoder *encoder,
mode->clock = mode->clock > 100000 ? 148500 : 74250;
else
mode->clock = 74250;
#endif
return 0;
}
......@@ -213,13 +224,21 @@ imx8mp_ldb_encoder_mode_valid(struct drm_encoder *encoder,
struct imx8mp_ldb_channel *imx8mp_ldb_ch =
enc_to_imx8mp_ldb_ch(encoder);
struct ldb_channel *ldb_ch = &imx8mp_ldb_ch->base;
#ifndef CONFIG_DRM_SECO_IMX8MP_LDB
struct imx8mp_ldb *imx8mp_ldb = imx8mp_ldb_ch->imx8mp_ldb;
struct ldb *ldb = &imx8mp_ldb->base;
#endif
/* it should be okay with a panel */
if (ldb_ch->panel)
return MODE_OK;
/*
* This excludes panels with clock not equal to:
* - 148.5MHz or 74.25MHz for Dual Channel
* - 74.25MHz for Single Channel
*/
#ifndef CONFIG_DRM_SECO_IMX8MP_LDB
/*
* Due to limited video PLL frequency points on i.MX8mp,
* we do mode valid check here.
......@@ -229,6 +248,7 @@ imx8mp_ldb_encoder_mode_valid(struct drm_encoder *encoder,
if (!ldb->dual && mode->clock != 74250)
return MODE_NOCLOCK;
#endif
return MODE_OK;
}
......
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