[C61] add pinctrl groups

arch/arm64/boot/dts/seco/seco-imx8mm-c61.dts

@@ -29,8 +29,6 @@
 
 	reg_usdhc2_vmmc: regulator-usdhc2 {
 		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
 		regulator-name = "VSD_3V3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
@@ -87,7 +85,7 @@
 	#size-cells = <0>;
 	fsl,spi-num-chipselects = <1>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
+	pinctrl-0 = <&pinctrl_ecspi2>;
 	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
@@ -366,30 +364,62 @@
 };
 
 &iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8        0x19
+			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27       0x0
+			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25       0x19
+			/* GPIO EXPANDER RESET */
+			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x19
+			/* USB HUB RESET */
+			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2        0x19
+			/* EDP Power Down Bridge Enable */
+			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11      0x19
+			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4        0x19
+			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5        0x19
+			/* LEDS */
+			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14       0x19 /* BLUE1 GATE GPIO 110*/
+			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16       0x19 /* RED1 GATE GPIO 112*/
+			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7        0x19 /* GREEN1 GATE GPIO 103 */
+
+			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28       0x0 /* RTC_INT */
+
+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7       0x19 /* ap ready */
+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8       0x19 /* wakeup_lte */
+		>;
+	};
+
 	pinctrl_csi_pwn: csi_pwn_grp {
 		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
+			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11		0x19
 		>;
 	};
 
 	pinctrl_csi_rst: csi_rst_grp {
 		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
-			MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59
+			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9		0x19
 		>;
 	};
 
-	pinctrl_ecspi2: ecspi2grp {
+	pinctrl_ecspi1: ecspi1grp {
 		fsl,pins = <
-			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82
-			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82
-			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x140
+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x140
+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x140
+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x140
 		>;
 	};
 
-	pinctrl_ecspi2_cs: ecspi2cs {
+	pinctrl_ecspi2: ecspi2grp {
 		fsl,pins = <
-			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x40000
+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x140
+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x140
+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x140
+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x140
+			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x140
 		>;
 	};
 
@@ -420,7 +450,6 @@
 			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
 			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
 			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
-			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
 		>;
 	};
 
@@ -451,6 +480,19 @@
 		>;
 	};
 
+	pinctrl_i2c3_gpio: i2c3gpiogrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x19 /* accelerometer interrupt */
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x400001c3
+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x400001c3
+		>;
+	};
+
 	pinctrl_mipi_dsi_en: mipi_dsi_en {
 		fsl,pins = <
 			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x16
@@ -459,21 +501,16 @@
 
 	pinctrl_pcie0: pcie0grp {
 		fsl,pins = <
-			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B	0x61 /* open drain, pull up */
-			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x41
-			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x41
+			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x19 /* pcie0 reset */
+			MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13		0x19 /* pcie0 clk gen enable */
 		>;
 	};
 
 	pinctrl_pdm: pdmgrp {
 		fsl,pins = <
-			MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK	0xd6
-			MX8MM_IOMUXC_SAI5_RXC_PDM_CLK		0xd6
-			MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC	0xd6
-			MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0	0xd6
-			MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1	0xd6
-			MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2	0xd6
-			MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3	0xd6
+			MX8MM_IOMUXC_SAI5_RXC_PDM_CLK           0xd6
+			MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2        0xd6
+			MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3        0xd6
 		>;
 	};
 
@@ -483,17 +520,10 @@
 		>;
 	};
 
-	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
-		>;
-	};
-
 	pinctrl_sai3: sai3grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
 			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
-			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
 			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
 		>;
 	};
@@ -518,14 +548,24 @@
 		fsl,pins = <
 			MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX           0x140
 			MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX           0x140
-			MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B         0x140
 			MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B        0x140
+			MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B         0x140
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX           0x140
+			MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX           0x140
+			MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B        0x140
+			MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B         0x140
 		>;
 	};
 
 	pinctrl_usdhc1_gpio: usdhc1grpgpio {
 		fsl,pins = <
-			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
+			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10        0x41
+			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0
 		>;
 	};
 
@@ -564,7 +604,8 @@
 
 	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
 		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x19
 		>;
 	};
 
@@ -655,7 +696,72 @@
 
 	pinctrl_wdog: wdoggrp {
 		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
+			MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21	0x19 /*WD_TRG*/
+			MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11	0x19 /*WD_EN*/
+		>;
+	};
+
+	pinctrl_bt_gpios: btgpiosgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x19
+		>;
+	};
+
+	pinctrl_can1_int: can1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30	0x41
+		>;
+	};
+
+	pinctrl_can2_int: can2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29	0x41
+		>;
+	};
+
+	pinctrl_touch_gpio: touchgpiogrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19	0x19 /* Touch reset */
+			MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20	0x19 /* Touch Interrupt */
+		>;
+	};
+
+	pinctrl_pwm1_out: pwm1outgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT	0x4d
+		>;
+	};
+
+	pinctrl_pwm2_out: pwm2outgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT	0x4d
+		>;
+	};
+
+	pinctrl_pwm3_out: pwm3outgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT	0x4d
+		>;
+	};
+
+	pinctrl_pwm4_out: pwm4outgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT	0x4d
+		>;
+	};
+
+	pinctrl_gsm_modem: gsmgrp {
+		fsl,pins = <
+			/* MODEM GSM */
+			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18	0x19 /* MODEM GSM PWRKEY_EN */
+			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12	0x19 /* MODEM USB_BOOT_EN */
+			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3	0x19 /* MODEM RESET_EN */
+		>;
+	};
+
+	pinctrl_pca6416_20: pca6416_20grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
 		>;
 	};
 };