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Commit 59a75483 authored by Yuri Mazzuoli's avatar Yuri Mazzuoli
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[C72 Mini][DTS] Add devicetree for C72 Mini 

- Import C72 common include file
- Add C72 Mini pinmuxing from kernel 5.4
(https://git.seco.com/edgehog/bsp/nxp/linux-seco-imx/-/blob/seco/develop/imx_5.4.70_2.3.0/arch/arm64/boot/dts/seco/seco-imx8mm-c72.dts)
parent 4d877084
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1 merge request!149[C72 Mini] Add support
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arch/arm64/boot/dts/seco/seco-imx8mm-c72.dts 0 → 100644
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/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "dt-bindings/net/ti-dp83867.h"
#include "include/imx8mm.dtsi"
#include "seco-imx8m-c72.dtsi"
/ {
model = "SECO i.MX8MM C72 board";
compatible = "fsl,imx8mm-evk", "seco,imx8mm-c72","fsl,imx8mm";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
seco-imx8mm-c72 {
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
/* USB HUB RESET */
MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19
/* WiFi */
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* WiFi CLK EN */
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* WiFi DISABLE */
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 /* WiFi WAKE */
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 /* M2 UART WAKE */
MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x19
MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x19
MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x19
MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x19
/* Wifi Audio */
MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x19
MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19
MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* THRMTRIP */
MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* GPIO 7 */
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* SMBALERT */
MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* EXT_WAKE */
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* BATLOW */
MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* ENET_INT */
MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* BT_IRQ */
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 /* M2 UART WAKE */
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 /* GPIO_0 */
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* GPIO_1 */
MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x19 /* GPIO_2 */
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* GPIO_3 */
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 /* GPIO_4 */
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 /* GPIO_5 */
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x19 /* GPIO_6 */
MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* GPIO_7 */
/* sn65dsi84 */
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x19 /* LCD_BRIDGE_EN */
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x1f /* LCD_BLEN */
MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x1f /* LCD_PPEN */
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_spi1: spi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x140
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x140
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x140
>;
};
pinctrl_can1_int: can1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x41
>;
};
pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* CS rtc */
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* CS can */
>;
};
pinctrl_can2_int: can2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x41
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x140
MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x140
MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x140
MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x140
>;
};
pinctrl_usdhc1_wlan: usdhc1grpgpio {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x19
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x19
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x19
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x19
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x19
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x19
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_pwm1_out: pwm1outgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x4d
>;
};
pinctrl_pwm2_out: pwm2outgrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x4d
>;
};
pinctrl_pwm3_out: pwm3outgrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x4d
>;
};
pinctrl_pwm4_out: pwm4outgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x4d
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* I2S_RST */
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
>;
};
pinctrl_gsm_modem: gsmgrp {
fsl,pins = <
/* MODEM GSM */
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* MODEM GSM PWRKEY_EN */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x19 /* MODEM USB_BOOT_EN */
MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* MODEM RESET_EN */
>;
};
pinctrl_can_int: cangrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x19 /* pcie0 clk gen enable */
>;
};
pinctrl_usbotg1_1: usbotg1grp-1 {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0xc6
>;
};
pinctrl_apx_wdog_trigger_pads: apx-pads-1 {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
>;
};
};
};
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