[C61] add LVDS sn65dsi84 support

* enabled at u-boot: seco_config tool

arch/arm64/boot/dts/seco/overlays/Makefile

@@ -34,6 +34,7 @@ dtbo-$(CONFIG_ARCH_MXC) += \
 	seco-imx8mm-c61-port2-gpios.dtbo\
 	seco-imx8mm-c61-port2-rs232.dtbo\
 	seco-imx8mm-c61-port2-rs485.dtbo\
+	seco-imx8mm-c61-video-sn65dsi84.dtbo\
 	seco-imx8mm-c61-video-sn65dsi86.dtbo\
 	seco-imx8mp-d18-hdmi.dtbo\
 	seco-imx8mp-d18-edp.dtbo\

arch/arm64/boot/dts/seco/overlays/seco-imx8mm-c61-video-sn65dsi84-overlay.dts

+/*
+ * Copyright 2021 SECO
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/drm_mipi_dsi.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/display/media-bus-format.h>
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "fsl,imx8mm-evk", "seco,imx8mm-c61", "fsl,imx8mm";
+
+/*  __________________________________________________________________________
+ * |                                                                          |
+ * |                               DSI-to-LVDS                                |
+ * |__________________________________________________________________________|
+ */
+
+	fragment@regulators {
+		target-path = "/";
+		__overlay__ {
+			reg_bkl_on: bklon {
+				compatible = "regulator-fixed";
+				regulator-name = "BKL ON";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+				off-on-delay = <20000>;
+				startup-delay-us = <1000>;
+				enable-active-high;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			reg_panel_on: panelon {
+				compatible = "regulator-fixed";
+				regulator-name = "PANEL ON";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
+				enable-active-high;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+
+	fragment@led_driver {
+		target = <&i2c2>;
+		__overlay__ {
+			mp3385_led_driver: mp3385@31 {
+				compatible = "seco,led_mp3385";
+				reg = <0x31>;
+				reg-val = <0xf1 0xc4 0x3b 0x03 0x7f 0xe0 0x01>;
+				status = "okay";
+			};
+		};
+	};
+
+	fragment@backlight {
+		target-path = "/";
+		__overlay__ {
+			backlight@0 {
+				compatible = "mp3385-backlight";
+				pwms = <&pwm1 0 5000000 0>; // 200Hz
+
+				brightness-levels = <0 100>;
+				num-interpolated-steps = <100>;
+				default-brightness-level = <80>;
+
+				enable-gpios = <&pca6416_20 9 GPIO_ACTIVE_HIGH>;
+				client-device = <&mp3385_led_driver>;
+			};
+		};
+	};
+
+	fragment@clock_gen {
+		target = <&i2c2>;
+		__overlay__ {
+			si5351a: clock-generator@60 {
+				compatible = "silabs,si5351a-msop";
+				status = "okay";
+				reg = <0x60>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#clock-cells = <1>;
+				/* connect xtal input to 27MHz reference */
+				clocks = <&osc_27m>;
+				clock-names = "xtal";
+				/* connect xtal input as source of pll0 and pll1 */
+				silabs,pll-source = <0 0>, <1 0>;
+				/*
+				* overwrite clkout0 configuration with:
+				* - 8mA output drive strength
+				* - pll0 as clock source of multisynth0
+				* - multisynth0 as clock source of output divider
+				* - multisynth0 can change pll0
+				* - set initial clock frequency of 74.25MHz
+				*/
+				clkout0 {
+						reg = <0>;
+						silabs,drive-strength = <8>;
+						silabs,multisynth-source = <0>;
+						silabs,clock-source = <0>;
+						silabs,pll-master;
+						silabs,pll-spread_spectrum-1_5;
+				};
+				/*
+				* overwrite clkout1 configuration with:
+				* - 4mA output drive strength
+				* - pll1 as clock source of multisynth1
+				* - multisynth1 as clock source of output divider
+				* - multisynth1 can change pll1
+				*/
+				clkout1 {
+						reg = <1>;
+						silabs,drive-strength = <8>;
+						silabs,multisynth-source = <1>;
+						silabs,clock-source = <0>;
+						silabs,pll-master;
+				};
+				/*
+				* overwrite clkout2 configuration with:
+				* - xtal as clock source of output divider
+				*/
+			};
+		};
+	};
+
+	fragment@panel {
+		target-path = "/";
+		__overlay__ {
+			panel_lvds: lvds_panel {
+				compatible = "seco-boe,ev156fhm", "panel-dpi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				no-hpd;
+
+				width-mm  = <68>;
+				height-mm = <121>;
+
+				prepare-ms   = <100>;
+				enable-ms    = <100>;
+				disable-ms   = <100>;
+				unprepare-ms = <100>;
+
+				bpc = <8>;
+				bus-format = <DT_MEDIA_BUS_FMT_RGB888_1X24>;
+
+				status = "okay";
+
+				panel-timing {
+					clock-frequency = <160000000>;
+					hactive = <1920>;
+					vactive = <1080>;
+					hfront-porch = <85>;
+					hsync-len = <10>;
+					hback-porch = <85>;
+					vfront-porch = <20>;
+					vsync-len = <10>;
+					vback-porch = <20>;
+				};
+
+				port@0 {
+					reg = <0>;
+					panel_in: endpoint {
+						remote-endpoint = <&bridge_to_panel>;
+					};
+				};
+			};
+		};
+	};
+
+	fragment@lcdif {
+		target = <&lcdif>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@mipi_dsi {
+		target = <&mipi_dsi>;
+		__overlay__ {
+			status = "okay";
+
+			port@1 {
+				mipi_to_bridge: endpoint {
+					remote-endpoint = <&bridge_to_mipi>;
+					attach-bridge;
+				};
+			};
+		};
+	};
+
+	fragment@lvds_bridge {
+		target = <&i2c4>;
+		__overlay__ {
+			lvds_bridge: sn65dsi84@2d {
+				compatible = "ti,sn65dsi84";
+				reg = <0x2d>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				pd-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+				bkl-gpios = <&pca6416_20 5 GPIO_ACTIVE_HIGH>;
+				vcc-supply = <&reg_bkl_on>;
+
+				lvds,datamap = "jeida";
+				lvds,dual-channel;
+				lvds,preserve-dsi-timings;
+
+				/*include/drm/drm_mipi_dsi.h*/
+				dsi,mode-flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM)>;
+				clocks = <&si5351a 0>;
+
+				status = "okay";
+
+				port@0 {
+					reg = <0>;
+					bridge_to_mipi: endpoint {
+						remote-endpoint = <&mipi_to_bridge>;
+					};
+				};
+				port@1 {
+					reg = <1>;
+					bridge_to_panel: endpoint {
+						remote-endpoint = <&panel_in>;
+					};
+				};
+			};
+		};
+	};
+
+};