/*****************************************************************************/
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)                                */
/*
 * Device-tree-file for the 7" FANNAL LVDS-display with the bulky name on 
 * SECO-E81 modules
 * see: C3007054491027A_SPEC V1.pdf
 * 
 * Copyright 2025 SECO NE    Dietmar Muscholik <dietmar.muscholik@seco.com>
 *
 *****************************************************************************/

#ifndef DISPLAY_E81_FN070PGRGUL037C_DTSI
#define DISPLAY_E81_FN070PGRGUL037C_DTSI

#include "e81-pinfunc.h"


// bridge
&edp2lvds {
	backlight = <&backlight0>;
	width-mm = <154>;
	height-mm = <86>;
	data-mapping = "jeida-24";
	status = "okay";

	// Note: The 35571428 Hz clock is used on the
	// i.MX93 for this display. The 33,3 MHz is
	// the calculated clock (1056 H x 525 V x 24 FPS).
	panel-timing {
		clock-frequency = <33300000>;
		//clock-frequency = <35571428>;
		hactive = <800>;
		hfront-porch = <210>;
		hsync-len = <6>;
		hback-porch = <40>;
		//htotal = <1056>;

		vactive = <480>;
		vfront-porch = <22>;
		vsync-len = <3>;
		vback-porch = <20>;
		//vtotal = <525>;

		vsync-active = <0>;
		hsync-active = <0>;
		de-active = <1>;
		pixelclk-active = <1>;
	};
};


// qualcomm edp
&mdss_edp0 {
	qcom,display-type = "primary";
	status = "okay";
};

// backlight
&backlight0 {
	status = "okay";
};

&pm8350c_pwm {
	status = "okay";
};

// connect to eDP
&mdss_mdp0 {
	connectors = <&smmu_sde_unsec &mdss_edp0>;
};

#endif