[E81][DTB] Include qcm6490-addons

qcm6490-addons.dtsi contains variuos additional stuff for the processor, as some reserved memory regions, firmware drivers, configs for memory dumps, thermal zones, dma heaps etc.

arch/arm64/boot/dts/seco/include/e81-common.dtsi

@@ -158,6 +158,13 @@ reg_qps615_rsex: rsex_qps {
 		vin-supply = <&reg_1v8_qps>;
 		regulator-enable-ramp-delay = <10000>;
 	};
+
+	can_clk: can-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <20000000>;
+		clock-output-names = "can-clk";
+	};
 };
 
 
@@ -656,6 +663,35 @@ &sdhc_1 {
 	status = "okay";
 };
 
+// spi
+&spi14 { // SPI 0
+	pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>, <&qup_spi14_cs1_gpio>;
+	pinctrl-names = "default";
+
+	cs-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>, <&tlmm 62 GPIO_ACTIVE_LOW>;
+	
+	status = "okay";
+};
+
+&spi3 { // SPI 1
+	status = "okay";
+};
+
+&spi12 { // SPI CAN
+	status = "okay";
+
+	can0: can@0 {
+		compatible = "microchip,mcp2518fd";
+		reg = <0>;
+		clocks = <&can_clk>;
+		spi-max-frequency = <5000000>;
+		interrupts-extended = <&tlmm 35 IRQ_TYPE_LEVEL_LOW>;
+		vdd-supply = <&vreg_l11c_3p3>;
+		xceiver-supply = <&vreg_l11c_3p3>;
+	};
+};
+
+
 // disable soundwire devices
 &swr0 {
 	status = "disabled";
@@ -944,6 +980,9 @@ lcd0_bklt_pwm: lcd0_bklt_pwm {
 };
 
 &tlmm {
+	// Remove the <48 4> (spi12 pins), which is set in qcm6490.dtsi
+    gpio-reserved-ranges = <32 2>;
+
 	pcie1_reset_n: pcie1-reset-n-state {
 		pins = "gpio2";
 		function = "gpio";
@@ -952,6 +991,11 @@ pcie1_reset_n: pcie1-reset-n-state {
 		bias-disable;
 	};
 
+	qup_spi14_cs1_gpio: qup-spi14-cs1-gpio-state {
+		pins = "gpio62";
+		function = "gpio";
+	};
+
 	qps615_intn_wol {
 		eth0_intn_wol_sig: eth0_intn_wol_sig {
 			mux {