diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index d849420582f60992d099bbff3864e2a9dd6e9e33..f303ebcb264c332f1fe686bcb1707bda142238ba 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1004,7 +1004,6 @@ sdhc_1: mmc@7c4000 {
 			power-domains = <&rpmhpd SC7280_CX>;
 			operating-points-v2 = <&sdhc1_opp_table>;
 
-			qcom,ice = <&ice_mmc>;
 			bus-width = <8>;
 			supports-cqe;
 			dma-coherent;
@@ -1038,13 +1037,6 @@ opp-384000000 {
 			};
 		};
 
-		ice_mmc: crypto@7c8000 {
-			compatible = "qcom,inline-crypto-engine";
-			reg = <0x0 0x7C8000 0x0 0x10000>;
-			qcom,ice-use-hwkm;
-			clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>;
-		};
-
 		gpi_dma0: dma-controller@900000 {
 			#dma-cells = <3>;
 			compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
diff --git a/arch/arm64/configs/qcom_defconfig b/arch/arm64/configs/qcom_defconfig
index b940e3e4fef537be54468da5dd7e895ef95e7356..be86822c1abd444596b8f95ce12c66385530eb65 100644
--- a/arch/arm64/configs/qcom_defconfig
+++ b/arch/arm64/configs/qcom_defconfig
@@ -528,7 +528,6 @@ CONFIG_TYPEC_MUX_GPIO_SBU=m
 CONFIG_TYPEC_MUX_NB7VPQ904M=m
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_MMC_CRYPTO=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ACPI=y
diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c
index 3fe4443009bca80f734cc70c4cf64d1fcdc41f6f..8fb9493f0b99e12b7b13d0f18161eec1d67ed8ef 100644
--- a/drivers/soc/qcom/ice.c
+++ b/drivers/soc/qcom/ice.c
@@ -66,6 +66,8 @@
 #define qcom_ice_readl(engine, reg)	\
 	readl((engine)->base + (reg))
 
+static bool qcom_ice_create_error;
+
 struct qcom_ice {
 	struct device *dev;
 	void __iomem *base;
@@ -609,17 +611,15 @@ struct qcom_ice *of_qcom_ice_get(struct device *dev)
 		goto out;
 	}
 
-	base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(base)) {
-		dev_warn(&pdev->dev, "ICE registers not found\n");
-		return PTR_ERR(base);
-	}
-
-	ice = qcom_ice_create(&pdev->dev, base);
-	if (IS_ERR(ice)) {
+	ice = platform_get_drvdata(pdev);
+	if (!ice) {
 		dev_err(dev, "Cannot get ice instance from %s\n",
 			dev_name(&pdev->dev));
 		platform_device_put(pdev);
+		if (qcom_ice_create_error)
+			ice = ERR_PTR(-EOPNOTSUPP);
+		else
+			ice = ERR_PTR(-EPROBE_DEFER);
 		goto out;
 	}
 
@@ -638,5 +638,44 @@ struct qcom_ice *of_qcom_ice_get(struct device *dev)
 }
 EXPORT_SYMBOL_GPL(of_qcom_ice_get);
 
+static int qcom_ice_probe(struct platform_device *pdev)
+{
+	struct qcom_ice *engine;
+	void __iomem *base;
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base)) {
+		dev_warn(&pdev->dev, "ICE registers not found\n");
+		return PTR_ERR(base);
+	}
+
+	engine = qcom_ice_create(&pdev->dev, base);
+
+	if (IS_ERR(engine)) {
+		qcom_ice_create_error = true;
+		return PTR_ERR(engine);
+	}
+
+	platform_set_drvdata(pdev, engine);
+
+	return 0;
+}
+
+static const struct of_device_id qcom_ice_of_match_table[] = {
+	{ .compatible = "qcom,inline-crypto-engine" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, qcom_ice_of_match_table);
+
+static struct platform_driver qcom_ice_driver = {
+	.probe	= qcom_ice_probe,
+	.driver = {
+		.name = "qcom-ice",
+		.of_match_table = qcom_ice_of_match_table,
+	},
+};
+
+module_platform_driver(qcom_ice_driver);
+
 MODULE_DESCRIPTION("Qualcomm Inline Crypto Engine driver");
 MODULE_LICENSE("GPL");