From d9025e95024dc66c81c82273d8e69b1212ea7414 Mon Sep 17 00:00:00 2001 From: Dietmar Muscholik <dietmar.muscholik@seco.com> Date: Thu, 6 Feb 2025 08:56:33 +0000 Subject: [PATCH] [E81] Remove empty subnodes of pcie1, reduce number of compiler warnings --- .../boot/dts/seco/include/e81-common.dtsi | 45 ++++++------------- 1 file changed, 13 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/seco/include/e81-common.dtsi b/arch/arm64/boot/dts/seco/include/e81-common.dtsi index 2da5238ffd094..bfd0b1cc4a6d0 100644 --- a/arch/arm64/boot/dts/seco/include/e81-common.dtsi +++ b/arch/arm64/boot/dts/seco/include/e81-common.dtsi @@ -576,7 +576,7 @@ &pcie0_phy { &pcie1 { pinctrl-0 = <&pcie1_reset_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; - + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; /* @@ -843,6 +843,7 @@ gpio_usb_hub_res { }; }; + // children of pcie1 (QPS615 switch) &pcie1 { dummy-supply = <&pcie_switch>; @@ -852,33 +853,17 @@ pcieport0: pcie@0 { #address-cells = <5>; #size-cells = <0>; - /* BDF 1.0.0 */ + // BDF 1.0.0 pcie1_bus1_dev0_fn0: pcie1_bus1_dev0_fn0 { reg = <0 0 0 0 0>; + #address-cells = <5>; + #size-cells = <0>; - /* BDF 2.1.0 */ - pcie1_bus2_dev1_fn0: pcie1_bus2_dev1_fn0 { - reg = <0x800 0x0 0x0 0x0 0x0>; - - /* BDF 3.0.0 */ - pcie1_bus3_dev0_fn0: pcie1_bus3_dev0_fn0 { - reg = <0x0 0x0 0x0 0x0 0x0>; - }; - }; - - /* BDF 2.2.0 */ - pcie1_bus2_dev2_fn0: pcie1_bus2_dev2_fn0 { - reg = <0x1000 0x0 0x0 0x0 0x0>; - - /* BDF 4.0.0 */ - pcie1_bus4_dev0_fn0: pcie1_bus4_dev0_fn0 { - reg = <0x0 0x0 0x0 0x0 0x0>; - }; - }; - - /* BDF 2.3.0 */ + // BDF 2.3.0 pcie1_bus2_dev3_fn0: pcie1_bus2_dev3_fn0 { reg = <0x1800 0x0 0x0 0x0 0x0>; + #address-cells = <5>; + #size-cells = <0>; // ETH0 qps615_eth0,qps615_eth0@pcie1_rp { @@ -886,7 +871,8 @@ qps615_eth0,qps615_eth0@pcie1_rp { // Interrupts are connected to QPS615 interrupt pins. // The qps-eth driver requires the pinctrl handle and - // interrupt to be set, so we assign it to an unused CPU pin. + // interrupt to be set, so we assign it to a CPU pin + // that is currently unused but will be used in REVC. pinctrl-names = "default"; pinctrl-0 = <ð0_intn_wol_sig>; interrupts-extended = <&tlmm 11 IRQ_TYPE_EDGE_FALLING>; @@ -898,12 +884,9 @@ qps615_eth0,qps615_eth0@pcie1_rp { /* power enable*/ phy-supply = <&vreg_l11b_1p504>; - - #address-cells = <1>; - #size-cells = <1>; }; - /* BDF 5.0.0 */ + // BDF 5.0.0 pcie1_bus5_dev0_fn0: pcie1_qps_eth0 { reg = <0x0 0x0 0x0 0x0 0x0>; qcom,iommu-group = <ð0_pci_iommu_group>; @@ -930,12 +913,9 @@ qps615_eth1,qps615_eth1@pcie1_rp { /* power enable*/ phy-supply = <&vreg_l17b_1p7>; - - #address-cells = <1>; - #size-cells = <1>; }; - /* BDF 5.0.1 */ + // BDF 5.0.1 pcie1_bus5_dev0_fn1: pcie1_qps_eth1 { reg = <0x100 0x0 0x0 0x0 0x0>; qcom,iommu-group = <ð1_pci_iommu_group>; @@ -948,6 +928,7 @@ eth1_pci_iommu_group: eth1_pci_iommu_group { }; }; + // pinctrl &pm8350c_gpios { // gpiochip1 -- GitLab