From 678b8a0711afecb25e5fb879afbc539e1a7bfd49 Mon Sep 17 00:00:00 2001 From: Oleksii Kutuzov <oleksii.kutuzov@seco.com> Date: Thu, 6 Feb 2025 14:40:00 +0000 Subject: [PATCH] [E81][DTB] Configure SPI0, SPI1, CAN_SPI --- .../boot/dts/seco/include/e81-common.dtsi | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/seco/include/e81-common.dtsi b/arch/arm64/boot/dts/seco/include/e81-common.dtsi index bdddeb5ccadfd..fc4750c1c2236 100644 --- a/arch/arm64/boot/dts/seco/include/e81-common.dtsi +++ b/arch/arm64/boot/dts/seco/include/e81-common.dtsi @@ -655,6 +655,25 @@ &sdhc_1 { status = "okay"; }; +// spi +&spi14 { // SPI 0 + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>, <&qup_spi14_cs1_gpio>; + pinctrl-names = "default"; + + cs-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>, <&tlmm 62 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&spi3 { // SPI 1 + status = "okay"; +}; + +&spi12 { // SPI CAN + status = "okay"; +}; + + // disable soundwire devices &swr0 { status = "disabled"; @@ -943,6 +962,9 @@ lcd0_bklt_pwm: lcd0_bklt_pwm { }; &tlmm { + // Remove the <48 4> (spi12 pins), which is set in qcm6490.dtsi + gpio-reserved-ranges = <32 2>; + pcie1_reset_n: pcie1-reset-n-state { pins = "gpio2"; function = "gpio"; @@ -951,6 +973,11 @@ pcie1_reset_n: pcie1-reset-n-state { bias-disable; }; + qup_spi14_cs1_gpio: qup-spi14-cs1-gpio-state { + pins = "gpio62"; + function = "gpio"; + }; + qps615_intn_wol { eth0_intn_wol_sig: eth0_intn_wol_sig { mux { -- GitLab