From f55654688059a337490915cd6f652d0585597f3d Mon Sep 17 00:00:00 2001
From: Han Xu <han.xu@nxp.com>
Date: Fri, 22 Feb 2019 10:44:56 -0600
Subject: [PATCH] MLK-20374: arm64: dts: change fspi PAD drive strength to
avoid overshoot
change the flexspi pad settings to pull_up and drive_low to avoid
overshoot.
Signed-off-by: Han Xu <han.xu@nxp.com>
---
.../boot/dts/freescale/fsl-imx8q-arm2.dtsi | 32 +++++++++----------
.../dts/freescale/fsl-imx8qm-ddr4-arm2.dts | 32 +++++++++----------
.../boot/dts/freescale/fsl-imx8qm-mek.dtsi | 32 +++++++++----------
.../boot/dts/freescale/fsl-imx8qxp-mek.dtsi | 32 +++++++++----------
.../dts/freescale/fsl-imx8x-17x17-val.dtsi | 12 +++----
.../boot/dts/freescale/fsl-imx8x-arm2.dtsi | 32 +++++++++----------
6 files changed, 86 insertions(+), 86 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi
index 108fa351f2af06..6415398f95459b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi
@@ -498,22 +498,22 @@
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
- SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
- SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c
- SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c
- SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c
- SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c
- SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c
- SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c
- SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c
- SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c
- SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c
- SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c
- SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c
- SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c
- SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c
- SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c
- SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c
+ SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
+ SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
+ SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
+ SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
+ SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
+ SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
+ SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
+ SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
+ SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
+ SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
+ SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
+ SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
+ SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
+ SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
+ SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
+ SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
>;
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts
index 96e18e98265f43..5a8487e269236f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts
@@ -478,22 +478,22 @@
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
- SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
- SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c
- SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c
- SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c
- SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c
- SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c
- SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c
- SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c
- SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c
- SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c
- SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c
- SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c
- SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c
- SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c
- SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c
- SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c
+ SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
+ SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
+ SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
+ SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
+ SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
+ SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
+ SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
+ SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
+ SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
+ SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
+ SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
+ SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
+ SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
+ SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
+ SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
+ SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
>;
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi
index 901e992ea48c6f..2f832826340a0f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi
@@ -337,22 +337,22 @@
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
- SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
- SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c
- SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c
- SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c
- SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c
- SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c
- SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c
- SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c
- SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c
- SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c
- SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c
- SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c
- SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c
- SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c
- SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c
- SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c
+ SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
+ SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
+ SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
+ SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
+ SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
+ SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
+ SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
+ SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
+ SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
+ SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
+ SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
+ SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
+ SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
+ SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
+ SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
+ SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
>;
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi
index aff1028744dec0..eaa7da4b07589e 100755
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi
@@ -422,22 +422,22 @@
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
- SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
- SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c
- SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c
- SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c
- SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c
- SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c
- SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c
- SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c
- SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c
- SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c
- SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c
- SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c
- SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c
- SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c
- SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c
- SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c
+ SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
+ SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
+ SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
+ SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
+ SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
+ SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
+ SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
+ SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
+ SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
+ SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
+ SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
+ SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
+ SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
+ SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
+ SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
+ SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
>;
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8x-17x17-val.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8x-17x17-val.dtsi
index f46ae0a00cd3ea..ac38be4998a6a7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8x-17x17-val.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8x-17x17-val.dtsi
@@ -42,12 +42,12 @@
imx8qxp-lpddr4-arm2 {
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
- SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
- SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c
- SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c
- SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c
- SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c
- SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c
+ SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
+ SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
+ SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
+ SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
+ SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
+ SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi
index 943f9522f4c930..9ff873574130d1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi
@@ -295,22 +295,22 @@
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
- SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
- SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c
- SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c
- SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c
- SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c
- SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c
- SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c
- SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c
- SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c
- SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c
- SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c
- SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c
- SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c
- SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c
- SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c
- SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c
+ SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
+ SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
+ SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
+ SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
+ SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
+ SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
+ SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
+ SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
+ SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
+ SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
+ SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
+ SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
+ SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
+ SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
+ SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
+ SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
>;
};
--
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