From db8a79d5ffd0f29377790332bbfa737bf63ffb3f Mon Sep 17 00:00:00 2001
From: Nicola Sparnacci <nicola.sparnacci@seco.com>
Date: Tue, 20 Feb 2024 15:19:11 +0000
Subject: [PATCH] [C57][NON-FUNCTIONAL] Convert tabs to spaces
---
arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts | 256 +++++++++---------
1 file changed, 128 insertions(+), 128 deletions(-)
diff --git a/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts b/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts
index bfd5e636500d35..ec23e6e92ef8f3 100644
--- a/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts
+++ b/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts
@@ -20,159 +20,159 @@
#include "include/imx8qxp.dtsi"
/ {
- model = "SECO i.MX8QXP C57";
- compatible = "fsl,imx8qxp-mek","seco,imx8qxp-c57","fsl,imx8qxp";
-
- chosen {
- bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
- stdout-path = &lpuart2;
- };
-
- aliases {
- serial0 = &lpuart0;
- serial1 = &lpuart1;
- serial2 = &lpuart2;
- serial3 = &lpuart3;
- mmc0 = &usdhc1;
- };
-
- cpus {
- A35_2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a35";
- reg = <0x0 0x2>;
- enable-method = "psci";
- next-level-cache = <&A35_L2>;
- };
-
- A35_3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a35";
- reg = <0x0 0x3>;
- enable-method = "psci";
- next-level-cache = <&A35_L2>;
- };
- };
-
- pmu {
- interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>;
- };
+ model = "SECO i.MX8QXP C57";
+ compatible = "fsl,imx8qxp-mek","seco,imx8qxp-c57","fsl,imx8qxp";
+
+ chosen {
+ bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
+ stdout-path = &lpuart2;
+ };
+
+ aliases {
+ serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial2 = &lpuart2;
+ serial3 = &lpuart3;
+ mmc0 = &usdhc1;
+ };
+
+ cpus {
+ A35_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ };
+
+ A35_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ };
+ };
+
+ pmu {
+ interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>;
+ };
};
&iomuxc {
- pinctrl-names = "default";
-
- imx8qxp-mek {
-
- pinctrl_lpuart0: lpuart0grp {
- fsl,pins = <
- IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
- IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
- >;
- };
-
-
- pinctrl_lpuart2: lpuart2grp {
- fsl,pins = <
- IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020
- IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020
- >;
- };
-
- pinctrl_lpuart3: lpuart3grp {
- fsl,pins = <
- IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
- IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
- >;
- };
+ pinctrl-names = "default";
+
+ imx8qxp-mek {
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
+ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
+ >;
+ };
+
+
+ pinctrl_lpuart2: lpuart2grp {
+ fsl,pins = <
+ IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020
+ IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020
+ >;
+ };
+
+ pinctrl_lpuart3: lpuart3grp {
+ fsl,pins = <
+ IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
+ IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
+ >;
+ };
pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
- fsl,pins = <
- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
- fsl,pins = <
- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
- >;
- };
- };
+ fsl,pins = <
+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ >;
+ };
+ };
};
&lpuart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart0>;
- uart-has-rtscts;
- status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+ uart-has-rtscts;
+ status = "okay";
};
&lpuart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart2>;
- status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart2>;
+ status = "okay";
};
&lpuart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart3>;
- status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart3>;
+ status = "okay";
};
&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
};
&usb3_phy {
- status = "okay";
+ status = "okay";
};
&usbotg3 {
- status = "okay";
+ status = "okay";
};
&usbotg3_cdns3 {
--
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