From d5fd407078ba64f70eb46d7cca219d0d40d2b9ee Mon Sep 17 00:00:00 2001
From: Clark Wang <xiaoning.wang@nxp.com>
Date: Fri, 15 Mar 2019 14:07:39 +0800
Subject: [PATCH] MLK-21153-2 ARM64: dts: add lpspi dma support for 8qxp
Add dma support for lpspi0 and lpspi2 modules on i.MX8QXP board.
Ensure the lpspi does not use cs-gpio in slave mode.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | 74 +++++++++++++++++--
.../fsl-imx8qxp-lpddr4-arm2-lpspi-slave.dts | 11 +++
2 files changed, 79 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
index 3ef17c3650b577..e5dd1a809f4cb8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
@@ -1009,6 +1009,25 @@
reg = <SC_R_SPI_0>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wakeup-irq = <336>;
+
+ pd_dma2_chan0: PD_LPSPI0_RX {
+ reg = <SC_R_DMA_2_CH0>;
+ power-domains =<&pd_dma_lpspi0>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_dma2_chan1: PD_LPSPI0_TX {
+ reg = <SC_R_DMA_2_CH1>;
+ power-domains =<&pd_dma2_chan0>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
pd_dma_lpspi1: PD_DMA_SPI_1 {
reg = <SC_R_SPI_1>;
@@ -1019,6 +1038,25 @@
reg = <SC_R_SPI_2>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wakeup-irq = <338>;
+
+ pd_dma2_chan4: PD_LPSPI2_RX {
+ reg = <SC_R_DMA_2_CH4>;
+ power-domains =<&pd_dma_lpspi2>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_dma2_chan5: PD_LPSPI2_TX {
+ reg = <SC_R_DMA_2_CH5>;
+ power-domains =<&pd_dma2_chan4>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
pd_dma_lpspi3: PD_DMA_SPI_3 {
reg = <SC_R_SPI_3>;
@@ -2719,7 +2757,9 @@
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QXP_SPI0_CLK>;
assigned-clock-rates = <20000000>;
- power-domains = <&pd_dma_lpspi0>;
+ power-domains = <&pd_dma2_chan1>;
+ dma-names = "tx","rx";
+ dmas = <&edma2 1 0 0>, <&edma2 0 0 1>;
status = "disabled";
};
@@ -2733,7 +2773,9 @@
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QXP_SPI2_CLK>;
assigned-clock-rates = <20000000>;
- power-domains = <&pd_dma_lpspi2>;
+ power-domains = <&pd_dma2_chan5>;
+ dma-names = "tx","rx";
+ dmas = <&edma2 5 0 0>, <&edma2 4 0 1>;
status = "disabled";
};
@@ -2804,7 +2846,15 @@
edma2: dma-controller@5a1f0000 {
compatible = "fsl,imx8qm-edma";
- reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */
+ reg = <0x0 0x5a200000 0x0 0x10000>, /* channel0 LPSPI0 rx */
+ <0x0 0x5a210000 0x0 0x10000>, /* channel1 LPSPI0 tx */
+ <0x0 0x5a220000 0x0 0x10000>, /* channel2 LPSPI1 rx */
+ <0x0 0x5a230000 0x0 0x10000>, /* channel3 LPSPI1 tx */
+ <0x0 0x5a240000 0x0 0x10000>, /* channel4 LPSPI2 rx */
+ <0x0 0x5a250000 0x0 0x10000>, /* channel5 LPSPI2 tx */
+ <0x0 0x5a260000 0x0 0x10000>, /* channel6 LPSPI3 rx */
+ <0x0 0x5a270000 0x0 0x10000>, /* channel7 LPSPI3 tx */
+ <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */
<0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */
<0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */
<0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */
@@ -2813,8 +2863,16 @@
<0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */
<0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */
#dma-cells = <3>;
- dma-channels = <8>;
- interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ dma-channels = <16>;
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
@@ -2822,7 +2880,11 @@
<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx",
+ interrupt-names = "edma2-chan0-rx", "edma2-chan1-tx",
+ "edma2-chan2-rx", "edma2-chan3-tx",
+ "edma2-chan4-rx", "edma2-chan5-tx",
+ "edma2-chan6-rx", "edma2-chan7-tx",
+ "edma2-chan8-rx", "edma2-chan9-tx",
"edma2-chan10-rx", "edma2-chan11-tx",
"edma2-chan12-rx", "edma2-chan13-tx",
"edma2-chan14-rx", "edma2-chan15-tx";
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi-slave.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi-slave.dts
index 7f3cf7082a937f..8c2661370de43f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi-slave.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi-slave.dts
@@ -16,6 +16,17 @@
/delete-node/&spidev0;
+&pinctrl_lpspi2 {
+ fsl,pins = <
+ SC_P_SPI2_SCK_ADMA_SPI2_SCK 0x0600004c
+ SC_P_SPI2_SDO_ADMA_SPI2_SDO 0x0600004c
+ SC_P_SPI2_SDI_ADMA_SPI2_SDI 0x0600004c
+ SC_P_SPI2_CS0_ADMA_SPI2_CS0 0x0600004c
+ >;
+};
+
&lpspi2 {
+ pinctrl-0 = <&pinctrl_lpspi2>;
+ /delete-property/ cs-gpios;
spi-slave;
};
--
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