From b8853aa3d912f47f649ad8de784ac3afd932437d Mon Sep 17 00:00:00 2001 From: Wu Zhangjin <wuzhangjin@gmail.com> Date: Tue, 13 Apr 2010 13:16:34 +0800 Subject: [PATCH] MIPS: Loongson: update cpu-feature-overrides.h Loongson doesn't support MIPSR2, therefore, MIPSR2 vectored interrupts (cpu_has_vint) and MIPSR2 external interrupt controller mode (cpu_has_veic) are 0. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1112/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> --- arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h index 16210cedd92987..675bd8641d5a1e 100644 --- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h @@ -52,6 +52,8 @@ #define cpu_has_tx39_cache 0 #define cpu_has_userlocal 0 #define cpu_has_vce 0 +#define cpu_has_veic 0 +#define cpu_has_vint 0 #define cpu_has_vtag_icache 0 #define cpu_has_watch 1 -- GitLab