From b7cec13f082fcc6e690559657d3f5493ea6eecb7 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@altera.com>
Date: Fri, 13 Dec 2013 16:38:28 -0600
Subject: [PATCH] clk: socfpga: Look for the GPIO_DB_CLK by its offset
After the patch:
"clk: socfpga: Map the clk manager base address in the clock driver"
The clk->name field in socfpga_clk_recalc_rate() was getting cleared. Replace
looking for the GPIO_DB_CLK by its divider offset instead.
Also rename the define SOCFPGA_DB_CLK_OFFSET -> SOCFPGA_GPIO_DB_CLK_OFFSET, as
this represents the GPIO_DB_CLK.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---
drivers/clk/socfpga/clk.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index 4fb52e1fc848a3..cba21a0823b6c3 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -51,7 +51,7 @@
#define SOCFPGA_NAND_CLK "nand_clk"
#define SOCFPGA_NAND_X_CLK "nand_x_clk"
#define SOCFPGA_MMC_CLK "sdmmc_clk"
-#define SOCFPGA_DB_CLK "gpio_db_clk"
+#define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
#define div_mask(width) ((1 << (width)) - 1)
#define streq(a, b) (strcmp((a), (b)) == 0)
@@ -234,7 +234,8 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
else if (socfpgaclk->div_reg) {
val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
val &= div_mask(socfpgaclk->width);
- if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
+ /* Check for GPIO_DB_CLK by its offset */
+ if ((int)socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
div = val + 1;
else
div = (1 << val);
--
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