From a467bb861c1bf26db1b75b4a8a37dbdbdcf42b14 Mon Sep 17 00:00:00 2001
From: Gianfranco Mariotti <gianfranco.mariotti@seco.com>
Date: Mon, 27 May 2024 15:01:54 +0200
Subject: [PATCH] [DRIVER] pll1443x: SSCG: fix build warning, on 32bit fix
warning as error
* fix possible uninitialized variables
* replace pointless do_div that on 32bit gives warning treated as error:
do_div is used for u64 dividends, but the math is on u32 values.
---
drivers/clk/imx/clk-pll14xx.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index a97d4b4b8ed70b..13efdac88f6b46 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -266,7 +266,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
const struct imx_pll14xx_rate_table *rate;
u32 tmp, div_val;
u32 sscg_en, mfr, mrr, sel_pf, sscg_val;
- u32 mfr_mrr, mf, mr_int, mr_frac;
+ u32 mfr_mrr, mf, mr;
struct device_node *np;
const char *clk_name;
char property[40];
@@ -315,7 +315,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
sprintf(property, "anatop-%s,sscg-enable", clk_name);
if (of_property_read_bool(np, property)) {
sscg_en = 1;
- mfr, mrr, sel_pf = -1;
+ mfr = mrr = sel_pf = -1;
/* 0 <= mfr <= 255, 1 <= mrr <= 63, 0 <= mrr * mfr <= 512 */
sprintf(property, "anatop-%s,mfr", clk_name);
@@ -376,10 +376,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
/* MF = Fin / p / mfr / (2^5) [Hz] */
mf = prate / (rate->pdiv * mfr * 32);
/* MR = mfr * mrr / m / (2^6) * 100 [%] */
- mr_int = mfr_mrr * 1000 / (rate->mdiv * 64);
- mr_frac = do_div(mr_int, 10);
+ mr = mfr_mrr * 1000 / (rate->mdiv * 64);
pr_info("%s: SSCG enabled for pll clk %s: MF: %dHz, MR: %d.%d%%\n",
- __func__, clk_name, mf, mr_int, mr_frac);
+ __func__, clk_name, mf, mr / 10, mr % 10);
}
}
}
--
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