From a04f2d9d3a08002a7712f18fcec43e2c4151d953 Mon Sep 17 00:00:00 2001
From: Lennert Buytenhek <buytenh@wantstofly.org>
Date: Wed, 22 Mar 2006 20:14:11 +0000
Subject: [PATCH] [ARM] 3381/1: ixp2000: fix slowport write timing control
 register fields

Patch from Lennert Buytenhek

The original version of the chip docs had the PW and SU fields in
the slowport write timing control register accidentally reversed.
This is mentioned in the errata (documentation change #4) and fixed
in newer docs.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 include/asm-arm/arch-ixp2000/ixp2000-regs.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index 2b57f91b4ebd89..ccae4bec92c583 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -353,8 +353,8 @@
  * Masks and shifts for various fields in the WTC and RTC registers.
  */
 #define	SLOWPORT_WRTC_MASK_HD		0x0003
-#define	SLOWPORT_WRTC_MASK_SU		0x003c
-#define	SLOWPORT_WRTC_MASK_PW		0x03c0
+#define	SLOWPORT_WRTC_MASK_PW		0x003c
+#define	SLOWPORT_WRTC_MASK_SU		0x03c0
 
 #define	SLOWPORT_WRTC_SHIFT_HD		0x00
 #define	SLOWPORT_WRTC_SHIFT_SU		0x02
-- 
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