diff --git a/arch/arm/boot/dts/seco/seco-imx6qdl-a75.dtsi b/arch/arm/boot/dts/seco/seco-imx6qdl-a75.dtsi
index 6580eab1a7960d0255fe8acbb2268746b5bcc029..d600494bdad262cfa7c0daf0544522428083995c 100644
--- a/arch/arm/boot/dts/seco/seco-imx6qdl-a75.dtsi
+++ b/arch/arm/boot/dts/seco/seco-imx6qdl-a75.dtsi
@@ -1,4 +1,3 @@
-
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/pwm/pwm.h>
@@ -18,6 +17,11 @@
 		reg = <0x10000000 0x40000000>;
 	};
 
+	rmii_clk: clock-rmii-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;  /* 25MHz for example */
+	};
 
 /*  __________________________________________________________________________
  * |                                                                          |
@@ -505,9 +509,11 @@
 	pinctrl-names        = "default";
 	pinctrl-0            = <&pinctrl_enet>;
 	phy-mode             = "rmii";
-	phy-reset-gpios      = <&gpio1 3 0>;
-	phy-reset-duration   = <20>;
-	phy-reset-post-delay = <100>;
+	clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
+	phy-handle           = <&ethphy0>;
+//	phy-reset-gpios      = <&gpio1 3 0>;
+//	phy-reset-duration   = <20>;
+//	phy-reset-post-delay = <100>;
 	fsl,num_tx_queues    = <3>;
 	fsl,num_rx_queues    = <3>;
 	fsl,magic-packet;
@@ -519,6 +525,9 @@
 
 		ethphy0: ethernet-phy@0 {
 			compatible = "ethernet-phy-ieee802.3-c22";
+			reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <20000>;
+			reset-deassert-us = <100000> ;
 			reg = <0>;
 			interrupt-parent = <&gpio1>;
 			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
@@ -893,7 +902,7 @@
 				/*  IRQ  */
 				MX6QDL_PAD_GPIO_2__GPIO1_IO02                0x1f071
 				MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER            0x1b0b0
-				MX6QDL_PAD_GPIO_16__ENET_REF_CLK             0x1b0b0
+				MX6QDL_PAD_GPIO_16__ENET_REF_CLK             0x4001b0a8
 				MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN           0x1b0b0
 				MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23          0x1b0b0
 			>;