From 92593df8800f3335d3f6d601a6de65d939bfc502 Mon Sep 17 00:00:00 2001
From: Richard Zhu <hongxing.zhu@nxp.com>
Date: Thu, 3 Jun 2021 16:30:37 +0800
Subject: [PATCH] LF-3464 clk: imx6q: specify the rate of eim_slow clock
Specify the clock rate of EIM_SLOW clock.
During the kernel updates, some codes of the following two commits are
missing. Re-collect them here again.
commit e01216753ee1 ("MLK-11602 arm: imx: set imx6qdl eim_slow clk to 135Mhz")
commit dc4d6e04f02a ("MLK-12013 arm: imx: set eim_slow clk to 132Mhz only for MXC_CPU_IMX6Q")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
---
drivers/clk/imx/clk-imx6q.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 34c2efc6907385..dae6d6e4e5b9d7 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -993,10 +993,15 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk);
clk_set_parent(hws[IMX6QDL_CLK_AXI_ALT_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk);
clk_set_parent(hws[IMX6QDL_CLK_AXI_SEL]->clk, hws[IMX6QDL_CLK_AXI_ALT_SEL]->clk);
+ /* set eim_slow to 135Mhz */
+ clk_set_rate(hws[IMX6QDL_CLK_EIM_SLOW]->clk, 135000000);
+
/* set epdc/pxp axi clock to 200Mhz */
clk_set_parent(hws[IMX6QDL_CLK_IPU2_SEL]->clk, hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk);
clk_set_rate(hws[IMX6QDL_CLK_IPU2]->clk, 200000000);
} else {
+ /* set eim_slow to 132Mhz */
+ clk_set_rate(hws[IMX6QDL_CLK_EIM_SLOW]->clk, 132000000);
clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk);
clk_set_parent(hws[IMX6QDL_CLK_IPU2_SEL]->clk, hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk);
--
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