diff --git a/arch/arm64/boot/dts/seco/overlays/Makefile b/arch/arm64/boot/dts/seco/overlays/Makefile
index 6a1607c63e84d14098d8079c0f51588a9ffa606b..13b76a76c81e2ce210f2bcec3657d26a273c62e1 100644
--- a/arch/arm64/boot/dts/seco/overlays/Makefile
+++ b/arch/arm64/boot/dts/seco/overlays/Makefile
@@ -51,7 +51,8 @@ dtbo-$(CONFIG_ARCH_MXC) += \
seco-imx8mn-c72-edp.dtbo\
seco-imx8mn-c72-lvds-dual-215.dtbo\
seco-imx8mn-c72-lvds-dual-156.dtbo \
- seco-imx8qxp-c57-lvds-1024x600.dtbo
+ seco-imx8qxp-c57-lvds-1024x600.dtbo \
+ seco-imx8qxp-c57-sn65dsi86-edp.dtbo
# seco-imx8qm-c26-dp.dtbo\
# seco-imx8qm-c26-lvds-single.dtbo\
diff --git a/arch/arm64/boot/dts/seco/overlays/seco-imx8qxp-c57-sn65dsi86-edp-overlay.dts b/arch/arm64/boot/dts/seco/overlays/seco-imx8qxp-c57-sn65dsi86-edp-overlay.dts
new file mode 100644
index 0000000000000000000000000000000000000000..be77a1e6495eb30476415e051a031798bd246d75
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/overlays/seco-imx8qxp-c57-sn65dsi86-edp-overlay.dts
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+
+/ {
+ compatible = "fsl,imx8qxp-mek","seco,imx8qxp-c57","fsl,imx8qxp";
+
+/* __________________________________________________________________________
+ * | |
+ * | eDP |
+ * |__________________________________________________________________________|
+ */
+
+ fragment@0 {
+ target-path = "/";
+ __overlay__ {
+ regulators {
+ mux_sel: mux_sel {
+ compatible = "regulator-fixed";
+ regulator-name = "MUX_SEL";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
+ enable-active-high;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&panel>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ fragment@2 {
+ target = <&i2c0_mipi_lvds0>;
+ __overlay__ {
+ status = "okay";
+ edp_bridge: sn65dsi86@2c {
+ status = "okay";
+ };
+ };
+ };
+
+ fragment@3 {
+ target = <&mipi0_dphy>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ fragment@4 {
+ target = <&mipi0_dsi_host>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+};
\ No newline at end of file
diff --git a/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts b/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts
index dae0134f9581cc19f5c286dbdc4c8398ccf9c379..ea784d914599bedbabfadd41ebd81e7bf4179467 100644
--- a/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts
+++ b/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts
@@ -29,6 +29,13 @@
stdout-path = &lpuart2;
};
+ osc_27m: clock_27 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ clock-output-names = "osc_27m";
+ };
+
aliases {
ethernet0 = &fec1;
ethernet1 = &fec2;
@@ -249,6 +256,20 @@
100>;
default-brightness-level = <90>;
};
+
+ panel: edp_panel {
+ status = "disabled";
+ compatible = "boe,ev156fhm", "panel-dpi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ panel_in: endpoint {
+ remote-endpoint = <&bridge_to_panel>;
+ };
+ };
+ };
};
&acm {
@@ -279,6 +300,10 @@
IMX8QXP_SPI3_SDI_LSIO_GPIO0_IO15 0x00000021
/*MUX_SEL LVDS*/
IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x00000021
+ /*EDP EN*/
+ IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000021
+ /*EDP_IRQ*/
+ IMX8QXP_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 0x0
/*EN_BCKL_DRV*/
IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x00000021
/*EN_VCC_LCD_SW*/
@@ -305,7 +330,6 @@
/*UART0 CTS/RTS*/
IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x16000020
IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x16000020
-
>;
};
@@ -623,7 +647,7 @@ gpio1: &lsio_gpio1 {
"UART0_RX",
"UART0_TX",
"UART2_TX",
- "UART2_RX";
+ "UART2_RX",
"DISPLAY_BRG_I2C_SCL",
"DISPLAY_BRG_I2C_SDA",
"PWM1",
@@ -1043,6 +1067,89 @@ gpio5: &lsio_gpio5 {
status = "okay";
};
+/* DSI/LVDS port 0 */
+&i2c0_mipi_lvds0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>;
+ clock-frequency = <100000>;
+ status = "disabled";
+
+ edp_bridge: sn65dsi86@2c {
+ status = "disabled";
+ compatible = "seco,sn65dsi86";
+ adi,dsi-lanes = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2c>;
+ dsi,max-lanes = <2>;
+ dsi,max-rate = <1500>;
+ pd-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>, <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ edp_irq-gpios = <&gpio1 1 IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&osc_27m>;
+ enable-hpd;
+ read-dp-rate-from-panel;
+ dsi,mode-flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM)>;
+ bkl_on_off_delay_range_us = <0 6000>;
+ lcd_on_off_delay_range_us = <0 200000>;
+
+ si-result = <0xb0 0x41>,
+ <0xb1 0x72>,
+ <0xb2 0xa4>,
+ <0xb3 0xc6>,
+ <0xb4 0xc6>,
+ <0xb5 0x32>,
+ <0xb6 0x74>,
+ <0xb8 0x33>,
+ <0xb9 0x75>,
+ <0xbc 0x34>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ bridge_to_mipi: endpoint {
+ remote-endpoint = <&mipi_to_bridge>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ bridge_to_panel: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+};
+
+&mipi0_dphy {
+ status = "disabled";
+};
+
+&mipi0_dsi_host {
+ status = "disabled";
+ pwr-delay = <10>;
+ ports{
+ port@1 {
+ reg = <1>;
+ mipi_to_bridge: endpoint {
+ remote-endpoint = <&bridge_to_mipi>;
+ };
+ };
+ };
+};
+
+&mipi1_dphy {
+ status = "disabled";
+};
+
+&mipi1_dsi_host {
+ status = "disabled";
+};
+
&dpu1 {
status = "okay";
};