diff --git a/arch/arm64/boot/dts/seco/Makefile b/arch/arm64/boot/dts/seco/Makefile
index 2df54afaac31dc31fddcda0d9c97c68d727f7be4..e6bd4fe8049e7d30bc19401910e7bb14b63a2158 100644
--- a/arch/arm64/boot/dts/seco/Makefile
+++ b/arch/arm64/boot/dts/seco/Makefile
@@ -8,7 +8,8 @@ dtb-$(CONFIG_ARCH_MXC) += seco-imx8mq-c12.dtb\
seco-imx8qm-c43.dtb\
seco-imx8mm-c61.dtb\
seco-imx8mn-c72.dtb\
- seco-imx8mp-d18.dtb
+ seco-imx8mp-d18.dtb\
+ seco-imx8qxp-c57.dtb
dts-dirs += overlays
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/seco/include/imx8dx.dtsi b/arch/arm64/boot/dts/seco/include/imx8dx.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..05a7f593e717f48f63525ed70a5ec086f036179d
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8dx.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2020 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8dxp.dtsi"
+
+&gpu_3d0 {
+ assigned-clock-rates = <372000000>, <372000000>;
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8dxp.dtsi b/arch/arm64/boot/dts/seco/include/imx8dxp.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..fba74a31184d285261939c59aeaf8045eae5117a
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8dxp.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8qxp.dtsi"
+
+&thermal_zones {
+ cpu-thermal0 {
+ cooling-maps {
+ map0 {
+ cooling-device =
+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
+
+&cpus {
+ /delete-node/ cpu@2;
+ /delete-node/ cpu@3;
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-adma.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..8b6f0fc00c5a6b4e2c272c737fae58781d5cde62
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-adma.dtsi
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&dma_ipg_clk {
+ clock-frequency = <160000000>;
+};
+
+&audio_ipg_clk {
+ clock-frequency = <160000000>;
+};
+
+&lpuart0 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+};
+
+&lpuart1 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+};
+
+&lpuart2 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+};
+
+&lpuart3 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+};
+
+&i2c0 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&i2c1 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&i2c2 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&i2c3 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&asrc0 {
+ compatible = "fsl,imx8qxp-asrc";
+};
+
+&asrc1 {
+ compatible = "fsl,imx8qxp-asrc";
+};
+
+&audio_subsys {
+
+ dsp: dsp@596e8000 {
+ compatible = "fsl,imx8qxp-hifi4";
+ reg = <0x596e8000 0x88000>;
+ clocks = <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "dsp_clk1", "dsp_clk2", "dsp_clk3";
+ firmware-name = "imx/dsp/hifi4.bin";
+ power-domains = <&pd IMX_SC_R_MU_13B>,
+ <&pd IMX_SC_R_DSP>,
+ <&pd IMX_SC_R_DSP_RAM>,
+ <&pd IMX_SC_R_IRQSTR_DSP>;
+ mbox-names = "tx0", "rx0", "rxdb0";
+ mboxes = <&lsio_mu13 0 0>,
+ <&lsio_mu13 1 0>,
+ <&lsio_mu13 3 0>;
+ status = "disabled";
+ };
+};
+
+&dma_subsys {
+ lcdif_mux_regs: mux-regs@5a170000 {
+ compatible = "fsl,imx8qxp-lcdif-mux-regs", "syscon";
+ reg = <0x5a170000 0x4>;
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-conn.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..f8ad22a7d1e22c86791a04cbdd9501ed5f9d2cf5
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-conn.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&usdhc1 {
+ compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
+};
+
+&usdhc2 {
+ compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
+};
+
+&fec1 {
+ compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec";
+};
+
+&fec2 {
+ compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec";
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qxp-ss-dc.dtsi b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-dc.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..a929c3a2341a70775a44d1fe4342bba10c6322ca
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-dc.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2019 NXP
+ */
+
+&dpu1 {
+ compatible = "fsl,imx8qxp-dpu";
+
+ dpu_disp0: port@0 {
+ reg = <0>;
+
+ dpu_disp0_ldb1_ch0: endpoint@0 {
+ remote-endpoint = <&ldb1_ch0>;
+ };
+
+ dpu_disp0_ldb1_ch1: endpoint@1 {
+ remote-endpoint = <&ldb1_ch1>;
+ };
+
+ dpu_disp0_mipi_dsi: endpoint@2 {
+ remote-endpoint = <&mipi0_dsi_in>;
+ };
+ };
+
+ dpu_disp1: port@1 {
+ reg = <1>;
+
+ dpu_disp1_ldb2_ch0: endpoint@0 {
+ remote-endpoint = <&ldb2_ch0>;
+ };
+
+ dpu_disp1_ldb2_ch1: endpoint@1 {
+ remote-endpoint = <&ldb2_ch1>;
+ };
+
+ dpu_disp1_mipi_dsi: endpoint@2 {
+ remote-endpoint = <&mipi1_dsi_in>;
+ };
+
+ dpu_disp1_lcdif: endpoint@3 {
+ };
+ };
+};
+
+/ {
+ display-subsystem {
+ compatible = "fsl,imx-display-subsystem";
+ ports = <&dpu_disp0>, <&dpu_disp1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qxp-ss-gpu.dtsi b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-gpu.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..424a25582434cf33222bc62817256005d8c21606
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-gpu.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&gpu0_subsys {
+ imx8_gpu_ss: imx8_gpu0_ss {
+ compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss";
+ cores = <&gpu_3d0>;
+ reg = <0x80000000 0x80000000>, <0x0 0x10000000>;
+ reg-names = "phys_baseaddr", "contiguous_mem";
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qxp-ss-hsio.dtsi b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-hsio.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..4fae19e5edb43b3e90918e786f20ad0de76d541f
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-hsio.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Richard Zhu <hongxing.zhu@nxp.com>
+ */
+
+&hsio_subsys {
+ phyx1_lpcg: clock-controller@5f090000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f090000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_refb_clk>, <&hsio_per_clk>,
+ <&hsio_per_clk>, <&hsio_per_clk>;
+ bit-offset = <0 4 8 16>;
+ clock-output-names = "hsio_phyx1_pclk",
+ "hsio_phyx1_epcs_tx_clk",
+ "hsio_phyx1_epcs_rx_clk",
+ "hsio_phyx1_apb_clk";
+ power-domains = <&pd IMX_SC_R_SERDES_1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qxp-ss-img.dtsi b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-img.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..b455ed6fc483bdbf1eba808c7a4156d7748cd569
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-img.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&csi1_pxl_lpcg {
+ status = "disabled";
+};
+
+&csi1_core_lpcg {
+ status = "disabled";
+};
+
+&csi1_esc_lpcg {
+ status = "disabled";
+};
+
+&irqsteer_csi1 {
+ status = "disabled";
+};
+
+&i2c_mipi_csi1 {
+ status = "disabled";
+};
+
+&gpio0_mipi_csi1 {
+ status = "disabled";
+};
+
+&mipi_csi_1 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-lsio.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..780b4440c757a2db67a51f41ec027bcde4903dfd
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-lsio.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&lsio_gpio0 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio1 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio2 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio3 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio4 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio5 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio6 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio7 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_mu0 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu1 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu2 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu3 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu4 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qxp-ss-lvds.dtsi b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-lvds.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..c8b5468f2d86c9295893aa79c426ce1375ae8bd1
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qxp-ss-lvds.dtsi
@@ -0,0 +1,425 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2019 NXP
+ */
+
+/ {
+ lvds_subsys: bus@56220000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x56220000 0x0 0x56220000 0x30000>;
+
+ mipi_ipg_clk: clock-mipi-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <120000000>;
+ clock-output-names = "mipi_ipg_clk";
+ };
+
+ mipi_pll_div2_clk: clock-mipi-div2-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <432000000>;
+ clock-output-names = "mipi_pll_div2_clk";
+ };
+
+ mipi0_lis_lpcg: clock-controller@56223000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi_ipg_clk>;
+ bit-offset = <16>;
+ clock-output-names = "mipi0_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ };
+
+ mipi0_pwm_lpcg: clock-controller@5622300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5622300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&mipi_ipg_clk>,
+ <&mipi_ipg_clk>;
+ bit-offset = <0 16 4>;
+ clock-output-names = "mipi0_pwm_lpcg_clk",
+ "mipi0_pwm_lpcg_ipg_clk",
+ "mipi0_pwm_lpcg_32k_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
+ };
+
+ mipi0_i2c0_lpcg: clock-controller@56223010 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223010 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&mipi_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "mipi0_i2c0_lpcg_clk",
+ "mipi0_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ };
+
+ mipi1_lis_lpcg: clock-controller@56243000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi_ipg_clk>;
+ bit-offset = <16>;
+ clock-output-names = "mipi1_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ };
+
+ mipi1_pwm_lpcg: clock-controller@5624300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5624300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&mipi_ipg_clk>,
+ <&mipi_ipg_clk>;
+ bit-offset = <0 16 4>;
+ clock-output-names = "mipi1_pwm_lpcg_clk",
+ "mipi1_pwm_lpcg_ipg_clk",
+ "mipi1_pwm_lpcg_32k_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+ };
+
+ mipi1_i2c0_lpcg: clock-controller@56243010 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243010 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&mipi_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "mipi1_i2c0_lpcg_clk",
+ "mipi1_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ };
+
+ irqsteer_mipi_lvds0: irqsteer@56220000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x56220000 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ clocks = <&mipi0_lis_lpcg 0>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ };
+
+ lvds_region1: lvds_region@56221000 {
+ compatible = "syscon";
+ reg = <0x56221000 0xf0>;
+ };
+
+ ldb1_phy: ldb_phy@56221000 {
+ compatible = "mixel,lvds-combo-phy";
+ reg = <0x56221000 0x100>, <0x56228000 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC3>;
+ clock-names = "phy";
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+ status = "disabled";
+ };
+
+ ldb1: ldb@562210e0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qxp-ldb";
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>,
+ <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>;
+ clock-names = "pixel", "bypass",
+ "aux_pixel", "aux_bypass";
+ power-domains = <&pd IMX_SC_R_LVDS_0>,
+ <&pd IMX_SC_R_LVDS_1>;
+ power-domain-names = "main", "aux";
+ gpr = <&lvds_region1>;
+ fsl,auxldb = <&ldb2>;
+ status = "disabled";
+
+ lvds-channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ phys = <&ldb1_phy>;
+ phy-names = "ldb_phy";
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ ldb1_ch0: endpoint {
+ remote-endpoint = <&dpu_disp0_ldb1_ch0>;
+ };
+ };
+ };
+
+ lvds-channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ phys = <&ldb1_phy>;
+ phy-names = "ldb_phy";
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ ldb1_ch1: endpoint {
+ remote-endpoint = <&dpu_disp0_ldb1_ch1>;
+ };
+ };
+ };
+ };
+
+ pwm_mipi_lvds0: pwm@56224000 {
+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+ reg = <0x56224000 0x1000>;
+ clocks = <&mipi0_pwm_lpcg 0>,
+ <&mipi0_pwm_lpcg 1>,
+ <&mipi0_pwm_lpcg 2>;
+ clock-names = "per", "ipg", "32k";
+ assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <2>;
+ power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
+ status = "disabled";
+ };
+
+ i2c0_mipi_lvds0: i2c@56226000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x56226000 0x1000>;
+ interrupts = <8>;
+ interrupt-parent = <&irqsteer_mipi_lvds0>;
+ clocks = <&mipi0_i2c0_lpcg 0>,
+ <&mipi0_i2c0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ status = "disabled";
+ };
+
+ mipi0_dphy: dphy@56228300 {
+ compatible = "fsl,imx8qm-mipi-dphy";
+ reg = <0x56228300 0x100>;
+ clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>;
+ clock-names = "phy_ref";
+ #phy-cells = <0>;
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ status = "disabled";
+ };
+
+ mipi0_dsi_host: dsi_host@56228000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qx-nwl-dsi";
+ reg = <0x56228000 0x300>;
+ clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>,
+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>,
+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&mipi_pll_div2_clk>;
+ clock-names = "pixel",
+ "bypass",
+ "phy_ref",
+ "tx_esc",
+ "rx_esc",
+ "phy_parent";
+ interrupts = <16>;
+ interrupt-parent = <&irqsteer_mipi_lvds0>;
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ phys = <&mipi0_dphy>;
+ phy-names = "dphy";
+ csr = <&lvds_region1>;
+ use-disp-ss;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+ mipi0_dsi_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dpu_disp0_mipi_dsi>;
+ };
+ };
+ };
+ };
+
+ irqsteer_mipi_lvds1: irqsteer@56240000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x56240000 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ clocks = <&mipi1_lis_lpcg 0>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ };
+
+ lvds_region2: lvds_region@56241000 {
+ compatible = "syscon";
+ reg = <0x56241000 0xf0>;
+ };
+
+ ldb2_phy: ldb_phy@56241000 {
+ compatible = "mixel,lvds-combo-phy";
+ reg = <0x56241000 0x100>, <0x56248000 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC3>;
+ clock-names = "phy";
+ power-domains = <&pd IMX_SC_R_LVDS_1>;
+ status = "disabled";
+ };
+
+ ldb2: ldb@562410e0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qxp-ldb";
+ clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>,
+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+ clock-names = "pixel", "bypass",
+ "aux_pixel", "aux_bypass";
+ power-domains = <&pd IMX_SC_R_LVDS_1>,
+ <&pd IMX_SC_R_LVDS_0>;
+ power-domain-names = "main", "aux";
+ gpr = <&lvds_region2>;
+ fsl,auxldb = <&ldb1>;
+ status = "disabled";
+
+ lvds-channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ phys = <&ldb2_phy>;
+ phy-names = "ldb_phy";
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ ldb2_ch0: endpoint {
+ remote-endpoint = <&dpu_disp1_ldb2_ch0>;
+ };
+ };
+ };
+
+ lvds-channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ phys = <&ldb2_phy>;
+ phy-names = "ldb_phy";
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ ldb2_ch1: endpoint {
+ remote-endpoint = <&dpu_disp1_ldb2_ch1>;
+ };
+ };
+ };
+ };
+
+ pwm_mipi_lvds1: pwm@56244000 {
+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+ reg = <0x56244000 0x1000>;
+ clocks = <&mipi1_pwm_lpcg 0>,
+ <&mipi1_pwm_lpcg 1>,
+ <&mipi1_pwm_lpcg 2>;
+ clock-names = "per", "ipg", "32k";
+ assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <2>;
+ power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+ status = "disabled";
+ };
+
+ i2c0_mipi_lvds1: i2c@56246000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x56246000 0x1000>;
+ interrupts = <8>;
+ interrupt-parent = <&irqsteer_mipi_lvds1>;
+ clocks = <&mipi1_i2c0_lpcg 0>,
+ <&mipi1_i2c0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ status = "disabled";
+ };
+
+ mipi1_dphy: dphy@56248300 {
+ compatible = "fsl,imx8qx-mipi-dphy";
+ reg = <0x56248300 0x100>;
+ clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>;
+ clock-names = "phy_ref";
+ #phy-cells = <0>;
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ status = "disabled";
+ };
+
+ mipi1_dsi_host: dsi_host@56248000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qx-nwl-dsi";
+ reg = <0x56248000 0x300>;
+ clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>,
+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>,
+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>,
+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>,
+ <&mipi_pll_div2_clk>;
+ clock-names = "pixel",
+ "bypass",
+ "phy_ref",
+ "tx_esc",
+ "rx_esc",
+ "phy_parent";
+ interrupts = <16>;
+ interrupt-parent = <&irqsteer_mipi_lvds1>;
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ phys = <&mipi1_dphy>;
+ phy-names = "dphy";
+ csr = <&lvds_region2>;
+ use-disp-ss;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+ mipi1_dsi_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dpu_disp1_mipi_dsi>;
+ };
+ };
+ };
+ };
+
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qxp.dtsi b/arch/arm64/boot/dts/seco/include/imx8qxp.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..084e62d71b66d8cb511a0e580228b9629b7d3840
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qxp.dtsi
@@ -0,0 +1,347 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/clock/imx8-clock.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/pads-imx8qxp.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ dpu0 = &dpu1;
+ ethernet0 = &fec1;
+ ethernet1 = &fec2;
+ gpio0 = &lsio_gpio0;
+ gpio1 = &lsio_gpio1;
+ gpio2 = &lsio_gpio2;
+ gpio3 = &lsio_gpio3;
+ gpio4 = &lsio_gpio4;
+ gpio5 = &lsio_gpio5;
+ gpio6 = &lsio_gpio6;
+ gpio7 = &lsio_gpio7;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ ldb0 = &ldb1;
+ ldb1 = &ldb2;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ mu0 = &lsio_mu0;
+ mu1 = &lsio_mu1;
+ mu2 = &lsio_mu2;
+ mu3 = &lsio_mu3;
+ mu4 = &lsio_mu4;
+ serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial2 = &lpuart2;
+ serial3 = &lpuart3;
+ isi0 = &isi_0;
+ isi1 = &isi_1;
+ isi2 = &isi_2;
+ isi3 = &isi_3;
+ isi4 = &isi_4;
+ isi5 = &isi_5;
+ isi6 = &isi_6;
+ isi7 = &isi_7;
+ csi0 = &mipi_csi_0;
+ can0 = &flexcan1;
+ can1 = &flexcan2;
+ can2 = &flexcan3;
+ i2c5 = &i2c_rpbus_5;
+ i2c12 = &i2c_rpbus_12;
+ i2c13 = &i2c_rpbus_13;
+ i2c14 = &i2c_rpbus_14;
+ i2c15 = &i2c_rpbus_15;
+ mipi_dsi0 = &mipi0_dsi_host;
+ mipi_dsi1 = &mipi1_dsi_host;
+ };
+
+ cpus: cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ /* We have 1 clusters with 4 Cortex-A35 cores */
+ A35_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
+ operating-points-v2 = <&a35_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ A35_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
+ operating-points-v2 = <&a35_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ A35_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
+ operating-points-v2 = <&a35_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ A35_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
+ operating-points-v2 = <&a35_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ A35_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ a35_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
+ gic: interrupt-controller@51a00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+ <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ scu {
+ compatible = "fsl,imx-scu";
+ mbox-names = "tx0",
+ "rx0",
+ "gip3";
+ mboxes = <&lsio_mu1 0 0
+ &lsio_mu1 1 0
+ &lsio_mu1 3 3>;
+
+ pd: imx8qx-pd {
+ compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
+ #power-domain-cells = <1>;
+ wakeup-irq = <235 236 237 258 262 267 271
+ 345 346 347 348>;
+ };
+
+ clk: clock-controller {
+ compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
+ #clock-cells = <2>;
+ clocks = <&xtal32k &xtal24m>;
+ clock-names = "xtal_32KHz", "xtal_24Mhz";
+ };
+
+ iomuxc: pinctrl {
+ compatible = "fsl,imx8qxp-iomuxc";
+ };
+
+ ocotp: imx8qx-ocotp {
+ compatible = "fsl,imx8qxp-scu-ocotp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ read-only;
+
+ fec_mac0: mac@2c4 {
+ reg = <0x2c4 6>;
+ };
+
+ fec_mac1: mac@2c6 {
+ reg = <0x2c6 6>;
+ };
+ };
+
+ scu_key: scu-key {
+ compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
+ linux,keycodes = <KEY_POWER>;
+ status = "disabled";
+ };
+
+ rtc: rtc {
+ compatible = "fsl,imx8qxp-sc-rtc";
+ };
+
+ secvio: secvio {
+ compatible = "fsl,imx-sc-secvio";
+ nvmem = <&ocotp>;
+ };
+
+ watchdog {
+ compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
+ timeout-sec = <60>;
+ };
+
+ tsens: thermal-sensor {
+ compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ soc {
+ compatible = "fsl,imx8qxp-soc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
+ };
+
+ clk_dummy: clock-dummy {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "clk_dummy";
+ };
+
+ xtal32k: clock-xtal32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xtal_32KHz";
+ };
+
+ xtal24m: clock-xtal24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal_24MHz";
+ };
+
+ thermal_zones: thermal-zones {
+ cpu-thermal0 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
+
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <107000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit0: trip1 {
+ temperature = <127000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ imx_ion {
+ compatible = "fsl,mxc-ion";
+ fsl,heap-id = <0>;
+ };
+
+ sc_pwrkey: sc-powerkey {
+ compatible = "fsl,imx8-pwrkey";
+ linux,keycode = <KEY_POWER>;
+ wakeup-source;
+ };
+
+ /* sorted in register address */
+ #include "imx8-ss-security.dtsi"
+ #include "imx8-ss-cm40.dtsi"
+ #include "imx8-ss-vpu.dtsi"
+ #include "imx8-ss-dc0.dtsi"
+ #include "imx8-ss-adma.dtsi"
+ #include "imx8-ss-conn.dtsi"
+ #include "imx8-ss-ddr.dtsi"
+ #include "imx8-ss-lsio.dtsi"
+ #include "imx8-ss-hsio.dtsi"
+ #include "imx8-ss-img.dtsi"
+ #include "imx8-ss-gpu0.dtsi"
+ #include "imx8-ss-lcdif.dtsi"
+};
+
+#include "imx8qxp-ss-adma.dtsi"
+#include "imx8qxp-ss-conn.dtsi"
+#include "imx8qxp-ss-lsio.dtsi"
+#include "imx8qxp-ss-hsio.dtsi"
+#include "imx8qxp-ss-img.dtsi"
+#include "imx8qxp-ss-dc.dtsi"
+#include "imx8qxp-ss-lvds.dtsi"
+#include "imx8qxp-ss-gpu.dtsi"
+
+&edma2 {
+ status = "okay";
+};
+
+&A35_0 {
+ operating-points = <
+ /* kHz uV*/
+ /* voltage is maintained by SCFW, so no need here */
+ 1200000 0
+ 900000 0
+ >;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
+ clock-latency = <61036>;
+ #cooling-cells = <2>;
+};
diff --git a/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts b/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts
new file mode 100644
index 0000000000000000000000000000000000000000..61d1423af9fcff13d911df40fc5fb809b4f45f07
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include <dt-bindings/drm_mipi_dsi.h>
+#include "dt-bindings/net/ti-dp83867.h"
+#include "include/imx8qxp.dtsi"
+
+/ {
+ model = "SECO i.MX8QXP C57";
+ compatible = "fsl,imx8qxp-mek","seco,imx8qxp-c57","fsl,imx8qxp";
+
+ chosen {
+ bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
+ stdout-path = &lpuart2;
+ };
+
+ aliases {
+ serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial2 = &lpuart2;
+ serial3 = &lpuart3;
+ };
+
+ cpus {
+ A35_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ };
+
+ A35_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ };
+ };
+
+ pmu {
+ interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>;
+ };
+
+};
+
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ imx8qxp-mek {
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
+ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
+ >;
+ };
+
+
+ pinctrl_lpuart2: lpuart2grp {
+ fsl,pins = <
+ IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020
+ IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020
+ >;
+ };
+
+ pinctrl_lpuart3: lpuart3grp {
+ fsl,pins = <
+ IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
+ IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
+ >;
+ };
+ };
+};
+
+&lpuart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&lpuart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart2>;
+ status = "okay";
+};
+
+&lpuart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart3>;
+ status = "okay";
+};
\ No newline at end of file