From 6714a8fa7d587b413a3fd02e9a46c0fd9ad51b83 Mon Sep 17 00:00:00 2001
From: Gianfranco Mariotti <gianfranco.mariotti@seco.com>
Date: Mon, 6 May 2024 16:50:21 +0200
Subject: [PATCH] [DRIVER] clk: imx: pll14xx: fix and use macros for FDIV_CTL
regs
Correct the definitions of "Divide and Fraction Data Control" registers,
and use them in the appropriate code sections.
---
drivers/clk/imx/clk-pll14xx.c | 33 +++++++++++++++++----------------
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index f7cfc5fead90f5..1303e2f5e0db89 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -15,7 +15,8 @@
#include "clk.h"
#define GNRL_CTL 0x0
-#define DIV_CTL 0x4
+#define FDIV_CTL0 0x4
+#define FDIV_CTL1 0x8
#define LOCK_STATUS BIT(31)
#define LOCK_SEL_MASK BIT(29)
#define CLKE_MASK BIT(11)
@@ -122,7 +123,7 @@ static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw,
u32 mdiv, pdiv, sdiv, pll_div;
u64 fvco = parent_rate;
- pll_div = readl_relaxed(pll->base + 4);
+ pll_div = readl_relaxed(pll->base + FDIV_CTL0);
mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
@@ -144,8 +145,8 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw,
long rate = 0;
int i;
- pll_div_ctl0 = readl_relaxed(pll->base + 4);
- pll_div_ctl1 = readl_relaxed(pll->base + 8);
+ pll_div_ctl0 = readl_relaxed(pll->base + FDIV_CTL0);
+ pll_div_ctl1 = readl_relaxed(pll->base + FDIV_CTL1);
mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
@@ -206,12 +207,12 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
return -EINVAL;
}
- tmp = readl_relaxed(pll->base + 4);
+ tmp = readl_relaxed(pll->base + FDIV_CTL0);
if (!clk_pll14xx_mp_change(rate, tmp)) {
tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
tmp |= rate->sdiv << SDIV_SHIFT;
- writel_relaxed(tmp, pll->base + 4);
+ writel_relaxed(tmp, pll->base + FDIV_CTL0);
return 0;
}
@@ -231,7 +232,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
(rate->sdiv << SDIV_SHIFT);
- writel_relaxed(div_val, pll->base + 0x4);
+ writel_relaxed(div_val, pll->base + FDIV_CTL0);
/*
* According to SPEC, t3 - t2 need to be greater than
@@ -272,15 +273,15 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
return -EINVAL;
}
- tmp = readl_relaxed(pll->base + 4);
+ tmp = readl_relaxed(pll->base + FDIV_CTL0);
if (!clk_pll14xx_mp_change(rate, tmp)) {
tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
tmp |= rate->sdiv << SDIV_SHIFT;
- writel_relaxed(tmp, pll->base + 4);
+ writel_relaxed(tmp, pll->base + FDIV_CTL0);
tmp = rate->kdiv << KDIV_SHIFT;
- writel_relaxed(tmp, pll->base + 8);
+ writel_relaxed(tmp, pll->base + FDIV_CTL1);
return 0;
}
@@ -296,8 +297,8 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
(rate->sdiv << SDIV_SHIFT);
- writel_relaxed(div_val, pll->base + 0x4);
- writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
+ writel_relaxed(div_val, pll->base + FDIV_CTL0);
+ writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + FDIV_CTL1);
/*
* According to SPEC, t3 - t2 need to be greater than
@@ -381,9 +382,9 @@ void clk_set_delta_k(struct clk_hw *hw, short int delta_k)
short int k;
u32 val;
- val = readl_relaxed(pll->base + 8);
+ val = readl_relaxed(pll->base + FDIV_CTL1);
k = (val & KDIV_MASK) + delta_k;
- writel_relaxed(k << KDIV_SHIFT, pll->base + 8);
+ writel_relaxed(k << KDIV_SHIFT, pll->base + FDIV_CTL1);
}
void clk_get_pll_setting(struct clk_hw *hw, u32 *pll_div_ctrl0,
@@ -391,8 +392,8 @@ void clk_get_pll_setting(struct clk_hw *hw, u32 *pll_div_ctrl0,
{
struct clk_pll14xx *pll = to_clk_pll14xx(hw);
- *pll_div_ctrl0 = readl_relaxed(pll->base + 4);
- *pll_div_ctrl1 = readl_relaxed(pll->base + 8);
+ *pll_div_ctrl0 = readl_relaxed(pll->base + FDIV_CTL0);
+ *pll_div_ctrl1 = readl_relaxed(pll->base + FDIV_CTL1);
}
static const struct clk_ops clk_pll1416x_ops = {
--
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