diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 9b1170658d600a9ea0c84f046e530319b083bca4..f6ed40f0e1633e38b51ebfe3ee20748a5e80006a 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -23,6 +23,7 @@ subdir-y += qcom
subdir-y += realtek
subdir-y += renesas
subdir-y += rockchip
+subdir-y += seco
subdir-y += socionext
subdir-y += sprd
subdir-y += synaptics
diff --git a/arch/arm64/boot/dts/seco/Makefile b/arch/arm64/boot/dts/seco/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..f373e26672d624c182861475692d68e28f474437
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/Makefile
@@ -0,0 +1,9 @@
+#
+# SECO Makefile
+#
+
+
+dts-dirs += overlays
+subdir-y := $(dts-dirs)
+DTC_FLAGS ?= -@ -H epapr
+
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-adma.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..841758bd2c8cd185a6b4f0ce9284e013fb02792e
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-adma.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include "imx8-ss-audio.dtsi"
+#include "imx8-ss-dma.dtsi"
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-audio.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..9c2157704ef065234c15deae2866201d773a8fad
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-audio.dtsi
@@ -0,0 +1,672 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+audio_subsys: bus@59000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x59000000 0x0 0x59000000 0x1000000>;
+
+ audio_ipg_clk: clock-audio-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <175000000>;
+ clock-output-names = "audio_ipg_clk";
+ };
+
+ edma0: dma-controller@591F0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x591f0000 0x10000>,
+ <0x59200000 0x10000>, /* asrc0 */
+ <0x59210000 0x10000>,
+ <0x59220000 0x10000>,
+ <0x59230000 0x10000>,
+ <0x59240000 0x10000>,
+ <0x59250000 0x10000>,
+ <0x59260000 0x10000>, /* esai0 rx */
+ <0x59270000 0x10000>, /* esai0 tx */
+ <0x59280000 0x10000>, /* spdif0 rx */
+ <0x59290000 0x10000>, /* spdif0 tx */
+ <0x592c0000 0x10000>, /* sai0 rx */
+ <0x592d0000 0x10000>, /* sai0 tx */
+ <0x592e0000 0x10000>, /* sai1 rx */
+ <0x592f0000 0x10000>, /* sai1 tx */
+ <0x59300000 0x10000>, /* sai2 rx */
+ <0x59310000 0x10000>, /* sai3 rx */
+ <0x59350000 0x10000>,
+ <0x59370000 0x10000>;
+ #dma-cells = <3>;
+ shared-interrupt;
+ dma-channels = <18>;
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */
+ <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */
+ "edma0-chan2-rx", "edma0-chan3-tx",
+ "edma0-chan4-tx", "edma0-chan5-tx",
+ "edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */
+ "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */
+ "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */
+ "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */
+ "edma0-chan16-rx", "edma0-chan17-rx", /* sai2, sai3 */
+ "edma0-chan21-tx", /* gpt5 */
+ "edma0-chan23-rx"; /* gpt7 */
+ power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
+ <&pd IMX_SC_R_DMA_0_CH1>,
+ <&pd IMX_SC_R_DMA_0_CH2>,
+ <&pd IMX_SC_R_DMA_0_CH3>,
+ <&pd IMX_SC_R_DMA_0_CH4>,
+ <&pd IMX_SC_R_DMA_0_CH5>,
+ <&pd IMX_SC_R_DMA_0_CH6>,
+ <&pd IMX_SC_R_DMA_0_CH7>,
+ <&pd IMX_SC_R_DMA_0_CH8>,
+ <&pd IMX_SC_R_DMA_0_CH9>,
+ <&pd IMX_SC_R_DMA_0_CH12>,
+ <&pd IMX_SC_R_DMA_0_CH13>,
+ <&pd IMX_SC_R_DMA_0_CH14>,
+ <&pd IMX_SC_R_DMA_0_CH15>,
+ <&pd IMX_SC_R_DMA_0_CH16>,
+ <&pd IMX_SC_R_DMA_0_CH17>,
+ <&pd IMX_SC_R_DMA_0_CH21>,
+ <&pd IMX_SC_R_DMA_0_CH23>;
+ power-domain-names = "edma0-chan0", "edma0-chan1",
+ "edma0-chan2", "edma0-chan3",
+ "edma0-chan4", "edma0-chan5",
+ "edma0-chan6", "edma0-chan7",
+ "edma0-chan8", "edma0-chan9",
+ "edma0-chan12", "edma0-chan13",
+ "edma0-chan14", "edma0-chan15",
+ "edma0-chan16", "edma0-chan17",
+ "edma0-chan21", "edma0-chan23";
+ status = "okay";
+ };
+
+ edma1: dma-controller@599F0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x599F0000 0x10000>,
+ <0x59A00000 0x10000>, /* asrc1 */
+ <0x59A10000 0x10000>,
+ <0x59A20000 0x10000>,
+ <0x59A30000 0x10000>,
+ <0x59A40000 0x10000>,
+ <0x59A50000 0x10000>,
+ <0x59A80000 0x10000>, /* sai4 rx */
+ <0x59A90000 0x10000>, /* sai4 tx */
+ <0x59AA0000 0x10000>; /* sai5 tx */
+ #dma-cells = <3>;
+ shared-interrupt;
+ dma-channels = <9>;
+ interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
+ interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */
+ "edma1-chan2-rx", "edma1-chan3-tx",
+ "edma1-chan4-tx", "edma1-chan5-tx",
+ "edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */
+ "edma1-chan10-tx"; /* sai5 */
+ power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
+ <&pd IMX_SC_R_DMA_1_CH1>,
+ <&pd IMX_SC_R_DMA_1_CH2>,
+ <&pd IMX_SC_R_DMA_1_CH3>,
+ <&pd IMX_SC_R_DMA_1_CH4>,
+ <&pd IMX_SC_R_DMA_1_CH5>,
+ <&pd IMX_SC_R_DMA_1_CH8>,
+ <&pd IMX_SC_R_DMA_1_CH9>,
+ <&pd IMX_SC_R_DMA_1_CH10>;
+ power-domain-names = "edma1-chan0", "edma1-chan1",
+ "edma1-chan2", "edma1-chan3",
+ "edma1-chan4", "edma1-chan5",
+ "edma1-chan8", "edma1-chan9",
+ "edma1-chan10";
+ status = "okay";
+ };
+
+ acm: acm@59e00000 {
+ compatible = "nxp,imx8qxp-acm";
+ reg = <0x59e00000 0x1D0000>;
+ #clock-cells = <1>;
+ power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
+ <&pd IMX_SC_R_AUDIO_CLK_1>,
+ <&pd IMX_SC_R_MCLK_OUT_0>,
+ <&pd IMX_SC_R_MCLK_OUT_1>,
+ <&pd IMX_SC_R_AUDIO_PLL_0>,
+ <&pd IMX_SC_R_AUDIO_PLL_1>,
+ <&pd IMX_SC_R_ASRC_0>,
+ <&pd IMX_SC_R_ASRC_1>,
+ <&pd IMX_SC_R_ESAI_0>,
+ <&pd IMX_SC_R_SAI_0>,
+ <&pd IMX_SC_R_SAI_1>,
+ <&pd IMX_SC_R_SAI_2>,
+ <&pd IMX_SC_R_SAI_3>,
+ <&pd IMX_SC_R_SAI_4>,
+ <&pd IMX_SC_R_SAI_5>,
+ <&pd IMX_SC_R_SPDIF_0>,
+ <&pd IMX_SC_R_MQS_0>;
+ };
+
+ asrc0: asrc@59000000 {
+ compatible = "fsl,imx8qm-asrc";
+ reg = <0x59000000 0x10000>;
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&asrc0_lpcg 0>,
+ <&asrc0_lpcg 0>,
+ <&aud_pll_div0_lpcg 0>,
+ <&aud_pll_div1_lpcg 0>,
+ <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+ <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "ipg", "mem",
+ "asrck_0", "asrck_1", "asrck_2", "asrck_3",
+ "asrck_4", "asrck_5", "asrck_6", "asrck_7",
+ "asrck_8", "asrck_9", "asrck_a", "asrck_b",
+ "asrck_c", "asrck_d", "asrck_e", "asrck_f",
+ "spba";
+ dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>,
+ <&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>;
+ dma-names = "rxa", "rxb", "rxc",
+ "txa", "txb", "txc";
+ fsl,asrc-rate = <8000>;
+ fsl,asrc-width = <16>;
+ fsl,asrc-clk-map = <0>;
+ power-domains = <&pd IMX_SC_R_ASRC_0>;
+ status = "disabled";
+ };
+
+ esai0: esai@59010000 {
+ compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai";
+ reg = <0x59010000 0x10000>;
+ interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&esai0_lpcg 1>,
+ <&esai0_lpcg 0>,
+ <&esai0_lpcg 1>,
+ <&clk_dummy>;
+ clock-names = "core", "extal", "fsys", "spba";
+ dmas = <&edma0 6 0 1>, <&edma0 7 0 0>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd IMX_SC_R_ESAI_0>;
+ status = "disabled";
+ };
+
+ spdif0: spdif@59020000 {
+ compatible = "fsl,imx8qm-spdif";
+ reg = <0x59020000 0x10000>;
+ interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
+ clocks = <&spdif0_lpcg 1>, /* core */
+ <&clk_dummy>, /* rxtx0 */
+ <&spdif0_lpcg 0>, /* rxtx1 */
+ <&clk_dummy>, /* rxtx2 */
+ <&clk_dummy>, /* rxtx3 */
+ <&clk_dummy>, /* rxtx4 */
+ <&audio_ipg_clk>, /* rxtx5 */
+ <&clk_dummy>, /* rxtx6 */
+ <&clk_dummy>, /* rxtx7 */
+ <&clk_dummy>; /* spba */
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7", "spba";
+ dmas = <&edma0 8 0 5>, <&edma0 9 0 4>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd IMX_SC_R_SPDIF_0>;
+ status = "disabled";
+ };
+
+ spdif1: spdif@59030000 {
+ compatible = "fsl,imx8qm-spdif";
+ reg = <0x59030000 0x10000>;
+ interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, /* rx */
+ <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; /* tx */
+ clocks = <&spdif1_lpcg 1>, /* core */
+ <&clk_dummy>, /* rxtx0 */
+ <&spdif1_lpcg 0>, /* rxtx1 */
+ <&clk_dummy>, /* rxtx2 */
+ <&clk_dummy>, /* rxtx3 */
+ <&clk_dummy>, /* rxtx4 */
+ <&audio_ipg_clk>, /* rxtx5 */
+ <&clk_dummy>, /* rxtx6 */
+ <&clk_dummy>, /* rxtx7 */
+ <&clk_dummy>; /* spba */
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7", "spba";
+ dmas = <&edma0 10 0 5>, <&edma0 11 0 4>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd IMX_SC_R_SPDIF_1>;
+ status = "disabled";
+ };
+
+ sai0: sai@59040000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59040000 0x10000>;
+ interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai0_lpcg 1>,
+ <&clk_dummy>,
+ <&sai0_lpcg 0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&edma0 12 0 1>, <&edma0 13 0 0>;
+ power-domains = <&pd IMX_SC_R_SAI_0>;
+ status = "disabled";
+ };
+
+ sai1: sai@59050000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59050000 0x10000>;
+ interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai1_lpcg 1>,
+ <&clk_dummy>,
+ <&sai1_lpcg 0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&edma0 14 0 1>, <&edma0 15 0 0>;
+ power-domains = <&pd IMX_SC_R_SAI_1>;
+ status = "disabled";
+ };
+
+ sai2: sai@59060000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59060000 0x10000>;
+ interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai2_lpcg 1>,
+ <&clk_dummy>,
+ <&sai2_lpcg 0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx";
+ dmas = <&edma0 16 0 1>;
+ power-domains = <&pd IMX_SC_R_SAI_2>;
+ status = "disabled";
+ };
+
+ sai3: sai@59070000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59070000 0x10000>;
+ interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai3_lpcg 1>,
+ <&clk_dummy>,
+ <&sai3_lpcg 0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx";
+ dmas = <&edma0 17 0 1>;
+ power-domains = <&pd IMX_SC_R_SAI_3>;
+ status = "disabled";
+ };
+
+ asrc1: asrc@59800000 {
+ compatible = "fsl,imx8qm-asrc";
+ reg = <0x59800000 0x10000>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&asrc1_lpcg 0>,
+ <&asrc1_lpcg 0>,
+ <&aud_pll_div0_lpcg 0>,
+ <&aud_pll_div1_lpcg 0>,
+ <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+ <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "ipg", "mem",
+ "asrck_0", "asrck_1", "asrck_2", "asrck_3",
+ "asrck_4", "asrck_5", "asrck_6", "asrck_7",
+ "asrck_8", "asrck_9", "asrck_a", "asrck_b",
+ "asrck_c", "asrck_d", "asrck_e", "asrck_f",
+ "spba";
+ dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>,
+ <&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>;
+ dma-names = "rxa", "rxb", "rxc",
+ "txa", "txb", "txc";
+ fsl,asrc-rate = <8000>;
+ fsl,asrc-width = <16>;
+ fsl,asrc-clk-map = <1>;
+ power-domains = <&pd IMX_SC_R_ASRC_1>;
+ status = "disabled";
+ };
+
+ sai4: sai@59820000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59820000 0x10000>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai4_lpcg 1>,
+ <&clk_dummy>,
+ <&sai4_lpcg 0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&edma1 8 0 1>, <&edma1 9 0 0>;
+ power-domains = <&pd IMX_SC_R_SAI_4>;
+ status = "disabled";
+ };
+
+ sai5: sai@59830000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59830000 0x10000>;
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai5_lpcg 1>,
+ <&clk_dummy>,
+ <&sai5_lpcg 0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx";
+ dmas = <&edma1 10 0 0>;
+ power-domains = <&pd IMX_SC_R_SAI_5>;
+ status = "disabled";
+ };
+
+ amix: amix@59840000 {
+ compatible = "fsl,imx8qm-audmix";
+ reg = <0x59840000 0x10000>;
+ clocks = <&amix_lpcg 0>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_AMIX>;
+ dais = <&sai4>, <&sai5>;
+ status = "disabled";
+ };
+
+ mqs: mqs@59850000 {
+ compatible = "fsl,imx8qm-mqs";
+ reg = <0x59850000 0x10000>;
+ clocks = <&mqs0_lpcg 1>,
+ <&mqs0_lpcg 0>;
+ clock-names = "core", "mclk";
+ power-domains = <&pd IMX_SC_R_MQS_0>;
+ status = "disabled";
+ };
+
+ asrc0_lpcg: clock-controller@59400000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59400000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&audio_ipg_clk>;
+ bit-offset = <16>;
+ clock-output-names = "asrc0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ASRC_0>;
+ };
+
+ esai0_lpcg: clock-controller@59410000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "esai0_lpcg_extal_clk",
+ "esai0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ESAI_0>;
+ };
+
+ spdif0_lpcg: clock-controller@59420000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59420000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "spdif0_lpcg_tx_clk",
+ "spdif0_lpcg_gclkw";
+ power-domains = <&pd IMX_SC_R_SPDIF_0>;
+ };
+
+ spdif1_lpcg: clock-controller@59430000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59430000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "spdif1_lpcg_tx_clk",
+ "spdif1_lpcg_gclkw";
+ power-domains = <&pd IMX_SC_R_SPDIF_1>;
+ status = "disabled";
+ };
+
+ sai0_lpcg: clock-controller@59440000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59440000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "sai0_lpcg_mclk",
+ "sai0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_0>;
+ };
+
+ sai1_lpcg: clock-controller@59450000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59450000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "sai1_lpcg_mclk",
+ "sai1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_1>;
+ };
+
+ sai2_lpcg: clock-controller@59460000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59460000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI2_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "sai2_lpcg_mclk",
+ "sai2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_2>;
+ };
+
+ sai3_lpcg: clock-controller@59470000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59470000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI3_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "sai3_lpcg_mclk",
+ "sai3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_3>;
+ };
+
+ dsp_lpcg: clock-controller@59580000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59580000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&audio_ipg_clk>,
+ <&audio_ipg_clk>,
+ <&audio_ipg_clk>;
+ bit-offset = <16 20 28>;
+ clock-output-names = "dsp_lpcg_adb_aclk",
+ "dsp_lpcg_ipg_clk",
+ "dsp_lpcg_core_clk";
+ power-domains = <&pd IMX_SC_R_DSP>;
+ };
+
+ dsp_ram_lpcg: clock-controller@59590000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59590000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&audio_ipg_clk>;
+ bit-offset = <16>;
+ clock-output-names = "dsp_ram_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_DSP_RAM>;
+ };
+
+ asrc1_lpcg: clock-controller@59c00000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c00000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&audio_ipg_clk>;
+ bit-offset = <16>;
+ clock-output-names = "asrc1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ASRC_1>;
+ };
+
+ sai4_lpcg: clock-controller@59c20000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "sai4_lpcg_mclk",
+ "sai4_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_4>;
+ };
+
+ sai5_lpcg: clock-controller@59c30000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c30000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "sai5_lpcg_mclk",
+ "sai5_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_5>;
+ };
+
+ amix_lpcg: clock-controller@59c40000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c40000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&audio_ipg_clk>;
+ bit-offset = <0>;
+ clock-output-names = "amix_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_AMIX>;
+ };
+
+ mqs0_lpcg: clock-controller@59c50000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c50000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "mqs0_lpcg_mclk",
+ "mqs0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MQS_0>;
+ };
+
+ aud_rec0_lpcg: clock-controller@59d00000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59d00000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
+ bit-offset = <0>;
+ clock-output-names = "aud_rec_clk0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>;
+ };
+
+ aud_rec1_lpcg: clock-controller@59d10000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59d10000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>;
+ bit-offset = <0>;
+ clock-output-names = "aud_rec_clk1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;
+ };
+
+ aud_pll_div0_lpcg: clock-controller@59d20000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59d20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>;
+ bit-offset = <0>;
+ clock-output-names = "aud_pll_div_clk0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>;
+ };
+
+ aud_pll_div1_lpcg: clock-controller@59d30000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59d30000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>;
+ bit-offset = <0>;
+ clock-output-names = "aud_pll_div_clk1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;
+ };
+
+ mclkout0_lpcg: clock-controller@59d50000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59d50000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_MCLKOUT0_SEL>;
+ bit-offset = <0>;
+ clock-output-names = "mclkout0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MCLK_OUT_0>;
+ };
+
+ mclkout1_lpcg: clock-controller@59d60000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59d60000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_MCLKOUT1_SEL>;
+ bit-offset = <0>;
+ clock-output-names = "mclkout1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MCLK_OUT_1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-cm40.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..2ca0eeff1f0704853c9e1b9fc5323ecfff04338d
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-cm40.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+cm40_subsys: bus@34000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x34000000 0x0 0x34000000 0x4000000>;
+
+ cm40_ipg_clk: clock-cm40-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <132000000>;
+ clock-output-names = "cm40_ipg_clk";
+ };
+
+ cm40_i2c: i2c@37230000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x37230000 0x1000>;
+ interrupts = <9 0>;
+ interrupt-parent = <&cm40_intmux>;
+ clocks = <&cm40_i2c_lpcg 0>,
+ <&cm40_i2c_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_M4_0_I2C>;
+ status = "disabled";
+ };
+
+ cm40_i2c_lpcg: clock-controller@37630000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x37630000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
+ <&cm40_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "cm40_lpcg_i2c_clk",
+ "cm40_lpcg_i2c_ipg_clk";
+ power-domains = <&pd IMX_SC_R_M4_0_I2C>;
+ };
+
+ cm40_intmux: intmux@37400000 {
+ compatible = "fsl,imx8qxp-intmux", "fsl,imx-intmux";
+ reg = <0x37400000 0x1000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ clocks = <&cm40_ipg_clk>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
+ status = "disabled";
+ };
+
+ cm40_lpuart: serial@37220000 {
+ compatible = "fsl,imx8qxp-lpuart";
+ reg = <0x37220000 0x1000>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&cm40_intmux>;
+ clocks = <&cm40_uart_lpcg 1>, <&cm40_uart_lpcg 0>;
+ clock-names = "ipg", "baud";
+ assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_M4_0_UART>;
+ status = "disabled";
+ };
+
+ cm40_uart_lpcg: clock-controller@37620000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x37620000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>,
+ <&cm40_ipg_clk>;
+ bit-offset = <0 4>;
+ clock-output-names = "cm40_lpcg_uart_clk",
+ "cm40_lpcg_uart_ipg_clk";
+ power-domains = <&pd IMX_SC_R_M4_0_UART>;
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-cm41.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-cm41.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..d0551f3815c4cb1ec8128ac55af1538acd010541
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-cm41.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+cm41_subsys: bus@38000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x38000000 0x0 0x38000000 0x4000000>;
+
+ cm41_ipg_clk: clock-cm41-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <132000000>;
+ clock-output-names = "cm41_ipg_clk";
+ };
+
+ cm41_i2c: i2c@3b230000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x3b230000 0x1000>;
+ interrupts = <9 0>;
+ interrupt-parent = <&cm41_intmux>;
+ clocks = <&cm41_i2c_lpcg 0>,
+ <&cm41_i2c_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_M4_1_I2C>;
+ status = "disabled";
+ };
+
+ cm41_i2c_lpcg: clock-controller@3b630000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x3b630000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>,
+ <&cm41_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "cm41_lpcg_i2c_clk",
+ "cm41_lpcg_i2c_ipg_clk";
+ power-domains = <&pd IMX_SC_R_M4_1_I2C>;
+ };
+
+ cm41_intmux: intmux@3b400000 {
+ compatible = "fsl,imx8qxp-intmux", "fsl,imx-intmux";
+ reg = <0x3b400000 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ clocks = <&cm41_ipg_clk>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_M4_1_INTMUX>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-conn.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..c97c8a6f525cf6e3afa7901ab6812c60c70a7281
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-conn.dtsi
@@ -0,0 +1,378 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+conn_subsys: bus@5b000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
+
+ conn_axi_clk: clock-conn-axi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <333333333>;
+ clock-output-names = "conn_axi_clk";
+ };
+
+ conn_ahb_clk: clock-conn-ahb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <166666666>;
+ clock-output-names = "conn_ahb_clk";
+ };
+
+ conn_ipg_clk: clock-conn-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <83333333>;
+ clock-output-names = "conn_ipg_clk";
+ };
+
+ conn_bch_clk: clock-conn-bch {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ clock-output-names = "conn_bch_clk";
+ };
+
+ usbotg1: usb@5b0d0000 {
+ compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb",
+ "fsl,imx27-usb";
+ reg = <0x5b0d0000 0x200>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc1 0>;
+ clocks = <&usb2_lpcg 0>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ power-domains = <&pd IMX_SC_R_USB_0>;
+ status = "disabled";
+ };
+
+ usbmisc1: usbmisc@5b0d0200 {
+ #index-cells = <1>;
+ compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
+ reg = <0x5b0d0200 0x200>;
+ };
+
+ usbphy1: usbphy@0x5b100000 {
+ compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy",
+ "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
+ reg = <0x5b100000 0x1000>;
+ clocks = <&usb2_lpcg 1>;
+ power-domains = <&pd IMX_SC_R_USB_0_PHY>;
+ status = "disabled";
+ };
+
+ usdhc1: mmc@5b010000 {
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x5b010000 0x10000>;
+ clocks = <&sdhc0_lpcg 1>,
+ <&sdhc0_lpcg 0>,
+ <&sdhc0_lpcg 2>;
+ clock-names = "ipg", "per", "ahb";
+ power-domains = <&pd IMX_SC_R_SDHC_0>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc2: mmc@5b020000 {
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x5b020000 0x10000>;
+ clocks = <&sdhc1_lpcg 1>,
+ <&sdhc1_lpcg 0>,
+ <&sdhc1_lpcg 2>;
+ clock-names = "ipg", "per", "ahb";
+ power-domains = <&pd IMX_SC_R_SDHC_1>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc3: mmc@5b030000 {
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x5b030000 0x10000>;
+ clocks = <&sdhc2_lpcg 1>,
+ <&sdhc2_lpcg 0>,
+ <&sdhc2_lpcg 2>;
+ clock-names = "ipg", "per", "ahb";
+ power-domains = <&pd IMX_SC_R_SDHC_2>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ fec1: ethernet@5b040000 {
+ reg = <0x5b040000 0x10000>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&enet0_lpcg 4>,
+ <&enet0_lpcg 2>,
+ <&enet0_lpcg 3>,
+ <&enet0_lpcg 0>,
+ <&enet0_lpcg 1>;
+ clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
+ assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
+ assigned-clock-rates = <250000000>, <125000000>;
+ fsl,num-tx-queues=<3>;
+ fsl,num-rx-queues=<3>;
+ power-domains = <&pd IMX_SC_R_ENET_0>;
+ status = "disabled";
+ };
+
+ fec2: ethernet@5b050000 {
+ reg = <0x5b050000 0x10000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&enet1_lpcg 4>,
+ <&enet1_lpcg 2>,
+ <&enet1_lpcg 3>,
+ <&enet1_lpcg 0>,
+ <&enet1_lpcg 1>;
+ clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
+ assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
+ assigned-clock-rates = <250000000>, <125000000>;
+ fsl,num-tx-queues=<3>;
+ fsl,num-rx-queues=<3>;
+ power-domains = <&pd IMX_SC_R_ENET_1>;
+ status = "disabled";
+ };
+
+ usb3_phy: usb-phy@5b160000 {
+ compatible = "nxp,salvo-phy";
+ reg = <0x5B160000 0x40000>;
+ clocks = <&usb3_lpcg 4>;
+ clock-names = "salvo_phy_clk";
+ power-domains = <&pd IMX_SC_R_USB_2_PHY>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usbotg3: usb@5b110000 {
+ compatible = "fsl,imx8qm-usb3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ reg = <0x5B110000 0x10000>;
+ clocks = <&usb3_lpcg 1>,
+ <&usb3_lpcg 0>,
+ <&usb3_lpcg 5>,
+ <&usb3_lpcg 2>,
+ <&usb3_lpcg 3>;
+ clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
+ "usb3_ipg_clk", "usb3_core_pclk";
+ assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
+ <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
+ assigned-clock-rates = <125000000>, <12000000>, <250000000>;
+ power-domains = <&pd IMX_SC_R_USB_2>;
+ status = "disabled";
+
+ usbotg3_cdns3: usb@5b120000 {
+ compatible = "cdns,usb3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host", "peripheral", "otg", "wakeup";
+ reg = <0x5B130000 0x10000>, /* memory area for HOST registers */
+ <0x5B140000 0x10000>, /* memory area for DEVICE registers */
+ <0x5B120000 0x10000>; /* memory area for OTG/DRD registers */
+ reg-names = "xhci", "dev", "otg";
+ phys = <&usb3_phy>;
+ phy-names = "cdns3,usb3-phy";
+ status = "disabled";
+ };
+ };
+
+ /* LPCG clocks */
+ sdhc0_lpcg: clock-controller@5b200000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b200000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
+ <&conn_ipg_clk>, <&conn_axi_clk>;
+ bit-offset = <0 16 20>;
+ clock-output-names = "sdhc0_lpcg_per_clk",
+ "sdhc0_lpcg_ipg_clk",
+ "sdhc0_lpcg_ahb_clk";
+ power-domains = <&pd IMX_SC_R_SDHC_0>;
+ };
+
+ sdhc1_lpcg: clock-controller@5b210000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b210000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
+ <&conn_ipg_clk>, <&conn_axi_clk>;
+ bit-offset = <0 16 20>;
+ clock-output-names = "sdhc1_lpcg_per_clk",
+ "sdhc1_lpcg_ipg_clk",
+ "sdhc1_lpcg_ahb_clk";
+ power-domains = <&pd IMX_SC_R_SDHC_1>;
+ };
+
+ sdhc2_lpcg: clock-controller@5b220000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b220000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
+ <&conn_ipg_clk>, <&conn_axi_clk>;
+ bit-offset = <0 16 20>;
+ clock-output-names = "sdhc2_lpcg_per_clk",
+ "sdhc2_lpcg_ipg_clk",
+ "sdhc2_lpcg_ahb_clk";
+ power-domains = <&pd IMX_SC_R_SDHC_2>;
+ };
+
+ enet0_lpcg: clock-controller@5b230000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b230000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
+ <&conn_axi_clk>,
+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>;
+ bit-offset = <0 4 8 12 16 20>;
+ clock-output-names = "enet0_lpcg_timer_clk",
+ "enet0_lpcg_txc_sampling_clk",
+ "enet0_lpcg_ahb_clk",
+ "enet0_lpcg_rgmii_txc_clk",
+ "enet0_lpcg_ipg_clk",
+ "enet0_lpcg_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_ENET_0>;
+ };
+
+ enet1_lpcg: clock-controller@5b240000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b240000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+ <&conn_axi_clk>,
+ <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>;
+ bit-offset = <0 4 8 12 16 20>;
+ clock-output-names = "enet1_lpcg_timer_clk",
+ "enet1_lpcg_txc_sampling_clk",
+ "enet1_lpcg_ahb_clk",
+ "enet1_lpcg_rgmii_txc_clk",
+ "enet1_lpcg_ipg_clk",
+ "enet1_lpcg_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_ENET_1>;
+ };
+
+ usb2_lpcg: clock-controller@5b270000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b270000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&conn_ahb_clk>, <&conn_ipg_clk>;
+ bit-offset = <24 28>;
+ clock-output-names = "usboh3_ahb_clk",
+ "usboh3_phy_ipg_clk";
+ power-domains = <&pd IMX_SC_R_USB_0_PHY>;
+ };
+
+ usb3_lpcg: clock-controller@5b280000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b280000 0x10000>;
+ #clock-cells = <1>;
+ bit-offset = <0 4 16 20 24 28>;
+ clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>,
+ <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
+ clock-output-names = "usb3_app_clk",
+ "usb3_lpm_clk",
+ "usb3_ipg_clk",
+ "usb3_core_pclk",
+ "usb3_phy_clk",
+ "usb3_aclk";
+ power-domains = <&pd IMX_SC_R_USB_2_PHY>;
+ };
+
+ rawnand_0_lpcg: clock-controller@5b290000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b290000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>,
+ <&conn_axi_clk>,
+ <&conn_axi_clk>;
+ bit-offset = <0 4 16 20>;
+ clock-output-names = "bch_clk",
+ "gpmi_clk",
+ "gpmi_apb_clk",
+ "bch_apb_clk";
+ power-domains = <&pd IMX_SC_R_NAND>;
+ };
+
+ rawnand_4_lpcg: clock-controller@5b290004 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b290004 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&conn_axi_clk>;
+ bit-offset = <16>;
+ clock-output-names = "apbhdma_hclk";
+ power-domains = <&pd IMX_SC_R_NAND>;
+ };
+
+ dma_apbh: dma-apbh@5b810000 {
+ compatible = "fsl,imx28-dma-apbh";
+ reg = <0x5b810000 0x2000>;
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&rawnand_4_lpcg 0>;
+ clock-names = "apbhdma_hclk";
+ power-domains = <&pd IMX_SC_R_NAND>;
+ };
+
+ gpmi: gpmi-nand@5b812000{
+ compatible = "fsl,imx8qxp-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+ clocks = <&rawnand_0_lpcg 1>,
+ <&rawnand_0_lpcg 2>,
+ <&rawnand_0_lpcg 0>,
+ <&rawnand_0_lpcg 3>;
+ clock-names = "gpmi_clk", "gpmi_apb_clk",
+ "bch_clk", "bch_apb_clk";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ power-domains = <&pd IMX_SC_R_NAND>;
+ assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>;
+ assigned-clock-rates = <50000000>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-dc0.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-dc0.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..eef051915fcc27805fbd13aab4456d0bf30c3b0d
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-dc0.dtsi
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019,2020 NXP
+ */
+
+dc0_subsys: bus@56000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x56000000 0x0 0x56000000 0x300000>;
+
+ dc0_cfg_clk: clock-dc-cfg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "dc0_cfg_clk";
+ };
+
+ dc0_axi_int_clk: clock-dc-axi-int {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ clock-output-names = "dc0_axi_int_clk";
+ };
+
+ dc0_axi_ext_clk: clock-dc-axi-ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "dc0_axi_ext_clk";
+ };
+
+ dc0_disp_lpcg: clock-controller@56010000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56010000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>,
+ <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>;
+ bit-offset = <0 4>;
+ clock-output-names = "dc0_disp0_lpcg_clk", "dc0_disp1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_dpr0_lpcg: clock-controller@56010018 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56010018 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc0_cfg_clk>,
+ <&dc0_axi_ext_clk>;
+ bit-offset = <16 20>;
+ clock-output-names = "dc0_dpr0_lpcg_apb_clk",
+ "dc0_dpr0_lpcg_b_clk";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_rtram0_lpcg: clock-controller@5601001c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5601001c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc0_axi_ext_clk>;
+ bit-offset = <0>;
+ clock-output-names = "dc0_rtram0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+
+ dc0_prg0_lpcg: clock-controller@56010020 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56010020 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc0_axi_ext_clk>,
+ <&dc0_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc0_prg0_lpcg_rtram_clk",
+ "dc0_prg0_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_prg1_lpcg: clock-controller@56010024 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56010024 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc0_axi_ext_clk>,
+ <&dc0_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc0_prg1_lpcg_rtram_clk",
+ "dc0_prg1_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_prg2_lpcg: clock-controller@56010028 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56010028 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc0_axi_ext_clk>,
+ <&dc0_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc0_prg2_lpcg_rtram_clk",
+ "dc0_prg2_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_dpr1_lpcg: clock-controller@5601002c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5601002c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc0_cfg_clk>,
+ <&dc0_axi_ext_clk>;
+ bit-offset = <16 20>;
+ clock-output-names = "dc0_dpr1_lpcg_apb_clk",
+ "dc0_dpr1_lpcg_b_clk";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_rtram1_lpcg: clock-controller@56010030 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56010030 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc0_axi_ext_clk>;
+ bit-offset = <0>;
+ clock-output-names = "dc0_rtram1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_prg3_lpcg: clock-controller@56010034 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56010034 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc0_axi_ext_clk>,
+ <&dc0_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc0_prg3_lpcg_rtram_clk",
+ "dc0_prg3_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_prg4_lpcg: clock-controller@56010038 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56010038 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc0_axi_ext_clk>,
+ <&dc0_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc0_prg4_lpcg_rtram_clk",
+ "dc0_prg4_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_prg5_lpcg: clock-controller@5601003c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5601003c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc0_axi_ext_clk>,
+ <&dc0_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc0_prg5_lpcg_rtram_clk",
+ "dc0_prg5_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_prg6_lpcg: clock-controller@56010040 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56010040 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc0_axi_ext_clk>,
+ <&dc0_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc0_prg6_lpcg_rtram_clk",
+ "dc0_prg6_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_prg7_lpcg: clock-controller@56010044 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56010044 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc0_axi_ext_clk>,
+ <&dc0_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc0_prg7_lpcg_rtram_clk",
+ "dc0_prg7_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_prg8_lpcg: clock-controller@56010048 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56010048 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc0_axi_ext_clk>,
+ <&dc0_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc0_prg8_lpcg_rtram_clk",
+ "dc0_prg8_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_irqsteer: irqsteer@56000000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x56000000 0x10000>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dc0_cfg_clk>;
+ clock-names = "ipg";
+ fsl,channel = <0>;
+ fsl,num-irqs = <512>;
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_pc: pixel-combiner@56020000 {
+ compatible = "fsl,imx8qxp-pixel-combiner",
+ "fsl,imx8qm-pixel-combiner";
+ reg = <0x56020000 0x10000>;
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg1: prg@56040000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x56040000 0x10000>;
+ clocks = <&dc0_prg0_lpcg 0>,
+ <&dc0_prg0_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg2: prg@56050000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x56050000 0x10000>;
+ clocks = <&dc0_prg1_lpcg 0>,
+ <&dc0_prg1_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg3: prg@56060000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x56060000 0x10000>;
+ clocks = <&dc0_prg2_lpcg 0>,
+ <&dc0_prg2_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg4: prg@56070000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x56070000 0x10000>;
+ clocks = <&dc0_prg3_lpcg 0>,
+ <&dc0_prg3_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg5: prg@56080000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x56080000 0x10000>;
+ clocks = <&dc0_prg4_lpcg 0>,
+ <&dc0_prg4_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg6: prg@56090000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x56090000 0x10000>;
+ clocks = <&dc0_prg5_lpcg 0>,
+ <&dc0_prg5_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg7: prg@560a0000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x560a0000 0x10000>;
+ clocks = <&dc0_prg6_lpcg 0>,
+ <&dc0_prg6_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg8: prg@560b0000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x560b0000 0x10000>;
+ clocks = <&dc0_prg7_lpcg 0>,
+ <&dc0_prg7_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg9: prg@560c0000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x560c0000 0x10000>;
+ clocks = <&dc0_prg8_lpcg 0>,
+ <&dc0_prg8_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_dpr1_channel1: dpr-channel@560d0000 {
+ compatible = "fsl,imx8qxp-dpr-channel",
+ "fsl,imx8qm-dpr-channel";
+ reg = <0x560d0000 0x10000>;
+ fsl,sc-resource = <IMX_SC_R_DC_0_BLIT0>;
+ fsl,prgs = <&dc0_prg1>;
+ clocks = <&dc0_dpr0_lpcg 0>,
+ <&dc0_dpr0_lpcg 1>,
+ <&dc0_rtram0_lpcg 0>;
+ clock-names = "apb", "b", "rtram";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_dpr1_channel2: dpr-channel@560e0000 {
+ compatible = "fsl,imx8qxp-dpr-channel",
+ "fsl,imx8qm-dpr-channel";
+ reg = <0x560e0000 0x10000>;
+ fsl,sc-resource = <IMX_SC_R_DC_0_BLIT1>;
+ fsl,prgs = <&dc0_prg2>, <&dc0_prg1>;
+ clocks = <&dc0_dpr0_lpcg 0>,
+ <&dc0_dpr0_lpcg 1>,
+ <&dc0_rtram0_lpcg 0>;
+ clock-names = "apb", "b", "rtram";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_dpr1_channel3: dpr-channel@560f0000 {
+ compatible = "fsl,imx8qxp-dpr-channel",
+ "fsl,imx8qm-dpr-channel";
+ reg = <0x560f0000 0x10000>;
+ fsl,sc-resource = <IMX_SC_R_DC_0_FRAC0>;
+ fsl,prgs = <&dc0_prg3>;
+ clocks = <&dc0_dpr0_lpcg 0>,
+ <&dc0_dpr0_lpcg 1>,
+ <&dc0_rtram0_lpcg 0>;
+ clock-names = "apb", "b", "rtram";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_dpr2_channel1: dpr-channel@56100000 {
+ compatible = "fsl,imx8qxp-dpr-channel",
+ "fsl,imx8qm-dpr-channel";
+ reg = <0x56100000 0x10000>;
+ fsl,sc-resource = <IMX_SC_R_DC_0_VIDEO0>;
+ fsl,prgs = <&dc0_prg4>, <&dc0_prg5>;
+ clocks = <&dc0_dpr1_lpcg 0>,
+ <&dc0_dpr1_lpcg 1>,
+ <&dc0_rtram1_lpcg 0>;
+ clock-names = "apb", "b", "rtram";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_dpr2_channel2: dpr-channel@56110000 {
+ compatible = "fsl,imx8qxp-dpr-channel",
+ "fsl,imx8qm-dpr-channel";
+ reg = <0x56110000 0x10000>;
+ fsl,sc-resource = <IMX_SC_R_DC_0_VIDEO1>;
+ fsl,prgs = <&dc0_prg6>, <&dc0_prg7>;
+ clocks = <&dc0_dpr1_lpcg 0>,
+ <&dc0_dpr1_lpcg 1>,
+ <&dc0_rtram1_lpcg 0>;
+ clock-names = "apb", "b", "rtram";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_dpr2_channel3: dpr-channel@56120000 {
+ compatible = "fsl,imx8qxp-dpr-channel",
+ "fsl,imx8qm-dpr-channel";
+ reg = <0x56120000 0x10000>;
+ fsl,sc-resource = <IMX_SC_R_DC_0_WARP>;
+ fsl,prgs = <&dc0_prg8>, <&dc0_prg9>;
+ clocks = <&dc0_dpr1_lpcg 0>,
+ <&dc0_dpr1_lpcg 1>,
+ <&dc0_rtram1_lpcg 0>;
+ clock-names = "apb", "b", "rtram";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dpu1: dpu@56180000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x56180000 0x40000>;
+ interrupt-parent = <&dc0_irqsteer>;
+ interrupts = <448>, <449>, <450>, <64>,
+ <65>, <66>, <67>, <68>,
+ <69>, <70>, <193>, <194>,
+ <195>, <196>, <197>, <72>,
+ <73>, <74>, <75>, <76>,
+ <77>, <78>, <79>, <80>,
+ <81>, <199>, <200>, <201>,
+ <202>, <203>, <204>, <205>,
+ <206>, <207>, <208>, <5>,
+ <0>, <1>, <2>, <3>,
+ <4>, <82>, <83>, <84>,
+ <85>, <209>, <210>, <211>,
+ <212>;
+ interrupt-names = "store9_shdload",
+ "store9_framecomplete",
+ "store9_seqcomplete",
+ "extdst0_shdload",
+ "extdst0_framecomplete",
+ "extdst0_seqcomplete",
+ "extdst4_shdload",
+ "extdst4_framecomplete",
+ "extdst4_seqcomplete",
+ "extdst1_shdload",
+ "extdst1_framecomplete",
+ "extdst1_seqcomplete",
+ "extdst5_shdload",
+ "extdst5_framecomplete",
+ "extdst5_seqcomplete",
+ "disengcfg_shdload0",
+ "disengcfg_framecomplete0",
+ "disengcfg_seqcomplete0",
+ "framegen0_int0",
+ "framegen0_int1",
+ "framegen0_int2",
+ "framegen0_int3",
+ "sig0_shdload",
+ "sig0_valid",
+ "sig0_error",
+ "disengcfg_shdload1",
+ "disengcfg_framecomplete1",
+ "disengcfg_seqcomplete1",
+ "framegen1_int0",
+ "framegen1_int1",
+ "framegen1_int2",
+ "framegen1_int3",
+ "sig1_shdload",
+ "sig1_valid",
+ "sig1_error",
+ "reserved",
+ "cmdseq_error",
+ "comctrl_sw0",
+ "comctrl_sw1",
+ "comctrl_sw2",
+ "comctrl_sw3",
+ "framegen0_primsync_on",
+ "framegen0_primsync_off",
+ "framegen0_secsync_on",
+ "framegen0_secsync_off",
+ "framegen1_primsync_on",
+ "framegen1_primsync_off",
+ "framegen1_secsync_on",
+ "framegen1_secsync_off";
+ clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>,
+ <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>,
+ <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>,
+ <&dc0_disp_lpcg 0>, <&dc0_disp_lpcg 1>;
+ clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1", "disp0_lpcg", "disp1_lpcg";
+ power-domains = <&pd IMX_SC_R_DC_0>,
+ <&pd IMX_SC_R_DC_0_PLL_0>,
+ <&pd IMX_SC_R_DC_0_PLL_1>;
+ power-domain-names = "dc", "pll0", "pll1";
+ fsl,dpr-channels = <&dc0_dpr1_channel1>,
+ <&dc0_dpr1_channel2>,
+ <&dc0_dpr1_channel3>,
+ <&dc0_dpr2_channel1>,
+ <&dc0_dpr2_channel2>,
+ <&dc0_dpr2_channel3>;
+ fsl,pixel-combiner = <&dc0_pc>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-dc1.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-dc1.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..c05a3eb7f9e57503586eccfa3c0c5d341dbf4239
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-dc1.dtsi
@@ -0,0 +1,488 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2019,2020 NXP
+ */
+
+dc1_subsys: bus@57000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x57000000 0x0 0x57000000 0x300000>;
+
+ dc1_cfg_clk: clock-dc-cfg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "dc1_cfg_clk";
+ };
+
+ dc1_axi_int_clk: clock-dc-axi-int {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ clock-output-names = "dc1_axi_int_clk";
+ };
+
+ dc1_axi_ext_clk: clock-dc-axi-ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "dc1_axi_ext_clk";
+ };
+
+ dc1_disp_lpcg: clock-controller@57010000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57010000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>,
+ <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>;
+ bit-offset = <0 4>;
+ clock-output-names = "dc1_disp0_lpcg_clk", "dc1_disp1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+ dc1_dpr0_lpcg: clock-controller@57010018 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57010018 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc1_cfg_clk>,
+ <&dc1_axi_ext_clk>;
+ bit-offset = <16 20>;
+ clock-output-names = "dc1_dpr0_lpcg_apb_clk",
+ "dc1_dpr0_lpcg_b_clk";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+ dc1_rtram0_lpcg: clock-controller@5701001c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5701001c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc1_axi_ext_clk>;
+ bit-offset = <0>;
+ clock-output-names = "dc1_rtram0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+
+ dc1_prg0_lpcg: clock-controller@57010020 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57010020 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc1_axi_ext_clk>,
+ <&dc1_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc1_prg0_lpcg_rtram_clk",
+ "dc1_prg0_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+ dc1_prg1_lpcg: clock-controller@57010024 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57010024 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc1_axi_ext_clk>,
+ <&dc1_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc1_prg1_lpcg_rtram_clk",
+ "dc1_prg1_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+ dc1_prg2_lpcg: clock-controller@57010028 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57010028 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc1_axi_ext_clk>,
+ <&dc1_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc1_prg2_lpcg_rtram_clk",
+ "dc1_prg2_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+ dc1_dpr1_lpcg: clock-controller@5701002c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5701002c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc1_cfg_clk>,
+ <&dc1_axi_ext_clk>;
+ bit-offset = <16 20>;
+ clock-output-names = "dc1_dpr1_lpcg_apb_clk",
+ "dc1_dpr1_lpcg_b_clk";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+ dc1_rtram1_lpcg: clock-controller@57010030 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57010030 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc1_axi_ext_clk>;
+ bit-offset = <0>;
+ clock-output-names = "dc1_rtram1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+ dc1_prg3_lpcg: clock-controller@57010034 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57010034 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc1_axi_ext_clk>,
+ <&dc1_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc1_prg3_lpcg_rtram_clk",
+ "dc1_prg3_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+ dc1_prg4_lpcg: clock-controller@57010038 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57010038 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc1_axi_ext_clk>,
+ <&dc1_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc1_prg4_lpcg_rtram_clk",
+ "dc1_prg4_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+ dc1_prg5_lpcg: clock-controller@5701003c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5701003c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc1_axi_ext_clk>,
+ <&dc1_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc1_prg5_lpcg_rtram_clk",
+ "dc1_prg5_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+ dc1_prg6_lpcg: clock-controller@57010040 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57010040 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc1_axi_ext_clk>,
+ <&dc1_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc1_prg6_lpcg_rtram_clk",
+ "dc1_prg6_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+ dc1_prg7_lpcg: clock-controller@57010044 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57010044 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc1_axi_ext_clk>,
+ <&dc1_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc1_prg7_lpcg_rtram_clk",
+ "dc1_prg7_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+ dc1_prg8_lpcg: clock-controller@57010048 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57010048 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dc1_axi_ext_clk>,
+ <&dc1_cfg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "dc1_prg8_lpcg_rtram_clk",
+ "dc1_prg8_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+ dc1_irqsteer: irqsteer@57000000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x57000000 0x10000>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dc1_cfg_clk>;
+ clock-names = "ipg";
+ fsl,channel = <0>;
+ fsl,num-irqs = <512>;
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ };
+
+ dc1_pc: pixel-combiner@57020000 {
+ compatible = "fsl,imx8qxp-pixel-combiner",
+ "fsl,imx8qm-pixel-combiner";
+ reg = <0x57020000 0x10000>;
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_prg1: prg@57040000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x57040000 0x10000>;
+ clocks = <&dc1_prg0_lpcg 0>,
+ <&dc1_prg0_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_prg2: prg@57050000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x57050000 0x10000>;
+ clocks = <&dc1_prg1_lpcg 0>,
+ <&dc1_prg1_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_prg3: prg@57060000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x57060000 0x10000>;
+ clocks = <&dc1_prg2_lpcg 0>,
+ <&dc1_prg2_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_prg4: prg@57070000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x57070000 0x10000>;
+ clocks = <&dc1_prg3_lpcg 0>,
+ <&dc1_prg3_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_prg5: prg@57080000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x57080000 0x10000>;
+ clocks = <&dc1_prg4_lpcg 0>,
+ <&dc1_prg4_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_prg6: prg@57090000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x57090000 0x10000>;
+ clocks = <&dc1_prg5_lpcg 0>,
+ <&dc1_prg5_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_prg7: prg@570a0000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x570a0000 0x10000>;
+ clocks = <&dc1_prg6_lpcg 0>,
+ <&dc1_prg6_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_prg8: prg@570b0000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x570b0000 0x10000>;
+ clocks = <&dc1_prg7_lpcg 0>,
+ <&dc1_prg7_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_prg9: prg@570c0000 {
+ compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+ reg = <0x570c0000 0x10000>;
+ clocks = <&dc1_prg8_lpcg 0>,
+ <&dc1_prg8_lpcg 1>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_dpr1_channel1: dpr-channel@570d0000 {
+ compatible = "fsl,imx8qxp-dpr-channel",
+ "fsl,imx8qm-dpr-channel";
+ reg = <0x570d0000 0x10000>;
+ fsl,sc-resource = <IMX_SC_R_DC_1_BLIT0>;
+ fsl,prgs = <&dc1_prg1>;
+ clocks = <&dc1_dpr0_lpcg 0>,
+ <&dc1_dpr0_lpcg 1>,
+ <&dc1_rtram0_lpcg 0>;
+ clock-names = "apb", "b", "rtram";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_dpr1_channel2: dpr-channel@570e0000 {
+ compatible = "fsl,imx8qxp-dpr-channel",
+ "fsl,imx8qm-dpr-channel";
+ reg = <0x570e0000 0x10000>;
+ fsl,sc-resource = <IMX_SC_R_DC_1_BLIT1>;
+ fsl,prgs = <&dc1_prg2>, <&dc1_prg1>;
+ clocks = <&dc1_dpr0_lpcg 0>,
+ <&dc1_dpr0_lpcg 1>,
+ <&dc1_rtram0_lpcg 0>;
+ clock-names = "apb", "b", "rtram";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_dpr1_channel3: dpr-channel@570f0000 {
+ compatible = "fsl,imx8qxp-dpr-channel",
+ "fsl,imx8qm-dpr-channel";
+ reg = <0x570f0000 0x10000>;
+ fsl,sc-resource = <IMX_SC_R_DC_1_FRAC0>;
+ fsl,prgs = <&dc1_prg3>;
+ clocks = <&dc1_dpr0_lpcg 0>,
+ <&dc1_dpr0_lpcg 1>,
+ <&dc1_rtram0_lpcg 0>;
+ clock-names = "apb", "b", "rtram";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_dpr2_channel1: dpr-channel@57100000 {
+ compatible = "fsl,imx8qxp-dpr-channel",
+ "fsl,imx8qm-dpr-channel";
+ reg = <0x57100000 0x10000>;
+ fsl,sc-resource = <IMX_SC_R_DC_1_VIDEO0>;
+ fsl,prgs = <&dc1_prg4>, <&dc1_prg5>;
+ clocks = <&dc1_dpr1_lpcg 0>,
+ <&dc1_dpr1_lpcg 1>,
+ <&dc1_rtram1_lpcg 0>;
+ clock-names = "apb", "b", "rtram";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_dpr2_channel2: dpr-channel@57110000 {
+ compatible = "fsl,imx8qxp-dpr-channel",
+ "fsl,imx8qm-dpr-channel";
+ reg = <0x57110000 0x10000>;
+ fsl,sc-resource = <IMX_SC_R_DC_1_VIDEO1>;
+ fsl,prgs = <&dc1_prg6>, <&dc1_prg7>;
+ clocks = <&dc1_dpr1_lpcg 0>,
+ <&dc1_dpr1_lpcg 1>,
+ <&dc1_rtram1_lpcg 0>;
+ clock-names = "apb", "b", "rtram";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dc1_dpr2_channel3: dpr-channel@57120000 {
+ compatible = "fsl,imx8qxp-dpr-channel",
+ "fsl,imx8qm-dpr-channel";
+ reg = <0x57120000 0x10000>;
+ fsl,sc-resource = <IMX_SC_R_DC_1_WARP>;
+ fsl,prgs = <&dc1_prg8>, <&dc1_prg9>;
+ clocks = <&dc1_dpr1_lpcg 0>,
+ <&dc1_dpr1_lpcg 1>,
+ <&dc1_rtram1_lpcg 0>;
+ clock-names = "apb", "b", "rtram";
+ power-domains = <&pd IMX_SC_R_DC_1>;
+ status = "disabled";
+ };
+
+ dpu2: dpu@57180000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x57180000 0x40000>;
+ interrupt-parent = <&dc1_irqsteer>;
+ interrupts = <448>, <449>, <450>, <64>,
+ <65>, <66>, <67>, <68>,
+ <69>, <70>, <193>, <194>,
+ <195>, <196>, <197>, <72>,
+ <73>, <74>, <75>, <76>,
+ <77>, <78>, <79>, <80>,
+ <81>, <199>, <200>, <201>,
+ <202>, <203>, <204>, <205>,
+ <206>, <207>, <208>, <5>,
+ <0>, <1>, <2>, <3>,
+ <4>, <82>, <83>, <84>,
+ <85>, <209>, <210>, <211>,
+ <212>;
+ interrupt-names = "store9_shdload",
+ "store9_framecomplete",
+ "store9_seqcomplete",
+ "extdst0_shdload",
+ "extdst0_framecomplete",
+ "extdst0_seqcomplete",
+ "extdst4_shdload",
+ "extdst4_framecomplete",
+ "extdst4_seqcomplete",
+ "extdst1_shdload",
+ "extdst1_framecomplete",
+ "extdst1_seqcomplete",
+ "extdst5_shdload",
+ "extdst5_framecomplete",
+ "extdst5_seqcomplete",
+ "disengcfg_shdload0",
+ "disengcfg_framecomplete0",
+ "disengcfg_seqcomplete0",
+ "framegen0_int0",
+ "framegen0_int1",
+ "framegen0_int2",
+ "framegen0_int3",
+ "sig0_shdload",
+ "sig0_valid",
+ "sig0_error",
+ "disengcfg_shdload1",
+ "disengcfg_framecomplete1",
+ "disengcfg_seqcomplete1",
+ "framegen1_int0",
+ "framegen1_int1",
+ "framegen1_int2",
+ "framegen1_int3",
+ "sig1_shdload",
+ "sig1_valid",
+ "sig1_error",
+ "reserved",
+ "cmdseq_error",
+ "comctrl_sw0",
+ "comctrl_sw1",
+ "comctrl_sw2",
+ "comctrl_sw3",
+ "framegen0_primsync_on",
+ "framegen0_primsync_off",
+ "framegen0_secsync_on",
+ "framegen0_secsync_off",
+ "framegen1_primsync_on",
+ "framegen1_primsync_off",
+ "framegen1_secsync_on",
+ "framegen1_secsync_off";
+ clocks = <&clk IMX_SC_R_DC_1_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_DC_1_PLL_1 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_DC_1_VIDEO0 IMX_SC_PM_CLK_BYPASS>,
+ <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>,
+ <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>,
+ <&dc1_disp_lpcg 0>, <&dc1_disp_lpcg 1>;
+ clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1", "disp0_lpcg", "disp1_lpcg";
+ power-domains = <&pd IMX_SC_R_DC_1>,
+ <&pd IMX_SC_R_DC_1_PLL_0>,
+ <&pd IMX_SC_R_DC_1_PLL_1>;
+ power-domain-names = "dc", "pll0", "pll1";
+ fsl,dpr-channels = <&dc1_dpr1_channel1>,
+ <&dc1_dpr1_channel2>,
+ <&dc1_dpr1_channel3>,
+ <&dc1_dpr2_channel1>,
+ <&dc1_dpr2_channel2>,
+ <&dc1_dpr2_channel3>;
+ fsl,pixel-combiner = <&dc1_pc>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-ddr.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-ddr.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..defe5a7f9d8786c7636b7e18922b12172b374aa7
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-ddr.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+ddr_subsys: bus@5c000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
+
+ ddr_pmu0: ddr-pmu@5c020000 {
+ compatible = "fsl,imx8-ddr-pmu";
+ reg = <0x5c020000 0x10000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-dma.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..6343f28de56e3e511498d6e180d4e8020358f686
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-dma.dtsi
@@ -0,0 +1,630 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+dma_subsys: bus@5a000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
+
+ dma_ipg_clk: clock-dma-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <120000000>;
+ clock-output-names = "dma_ipg_clk";
+ };
+
+ lpspi0: spi@5a000000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi0_lpcg 0>,
+ <&spi0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <20000000>;
+ power-domains = <&pd IMX_SC_R_SPI_0>;
+ dma-names = "tx","rx";
+ dmas = <&edma2 1 0 0>, <&edma2 0 0 1>;
+ status = "disabled";
+ };
+
+ lpspi1: spi@5a010000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a010000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi1_lpcg 0>,
+ <&spi1_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_1>;
+ dma-names = "tx","rx";
+ dmas = <&edma2 3 0 0>, <&edma2 2 0 1>;
+ status = "disabled";
+ };
+
+ lpspi2: spi@5a020000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a020000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi2_lpcg 0>,
+ <&spi2_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_2>;
+ dma-names = "tx","rx";
+ dmas = <&edma2 5 0 0>, <&edma2 4 0 1>;
+ status = "disabled";
+ };
+
+ lpspi3: spi@5a030000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a030000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi3_lpcg 0>,
+ <&spi3_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_3>;
+ dma-names = "tx","rx";
+ dmas = <&edma2 7 0 0>, <&edma2 6 0 1>;
+ status = "disabled";
+ };
+
+ lpuart0: serial@5a060000 {
+ reg = <0x5a060000 0x1000>;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&uart0_lpcg 1>, <&uart0_lpcg 0>;
+ clock-names = "ipg", "baud";
+ assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&pd IMX_SC_R_UART_0>;
+ status = "disabled";
+ };
+
+ lpuart1: serial@5a070000 {
+ reg = <0x5a070000 0x1000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&uart1_lpcg 1>, <&uart1_lpcg 0>;
+ clock-names = "ipg", "baud";
+ assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&pd IMX_SC_R_UART_1>;
+ power-domain-names = "uart";
+ dma-names = "tx","rx";
+ dmas = <&edma2 11 0 0>,
+ <&edma2 10 0 1>;
+ status = "disabled";
+ };
+
+ lpuart2: serial@5a080000 {
+ reg = <0x5a080000 0x1000>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&uart2_lpcg 1>, <&uart2_lpcg 0>;
+ clock-names = "ipg", "baud";
+ assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&pd IMX_SC_R_UART_2>;
+ power-domain-names = "uart";
+ dma-names = "tx","rx";
+ dmas = <&edma2 13 0 0>,
+ <&edma2 12 0 1>;
+ status = "disabled";
+ };
+
+ lpuart3: serial@5a090000 {
+ reg = <0x5a090000 0x1000>;
+ interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&uart3_lpcg 1>, <&uart3_lpcg 0>;
+ clock-names = "ipg", "baud";
+ assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&pd IMX_SC_R_UART_3>;
+ power-domain-names = "uart";
+ dma-names = "tx","rx";
+ dmas = <&edma2 15 0 0>,
+ <&edma2 14 0 1>;
+ status = "disabled";
+ };
+
+ emvsim0: sim0@5a0d0000 {
+ compatible = "fsl,imx8-emvsim";
+ reg = <0x5a0d0000 0x10000>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&emvsim0_lpcg 0>,
+ <&emvsim0_lpcg 1>;
+ clock-names = "sim", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_EMVSIM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_EMVSIM_0>, <&pd IMX_SC_R_BOARD_R2>;
+ power-domain-names = "sim_pd", "sim_aux_pd";
+ status = "disabled";
+ };
+
+ edma2: dma-controller@5a1f0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x5a1f0000 0x10000>,
+ <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */
+ <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */
+ <0x5a220000 0x10000>, /* channel2 LPSPI1 rx */
+ <0x5a230000 0x10000>, /* channel3 LPSPI1 tx */
+ <0x5a240000 0x10000>, /* channel4 LPSPI2 rx */
+ <0x5a250000 0x10000>, /* channel5 LPSPI2 tx */
+ <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */
+ <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */
+ <0x5a280000 0x10000>, /* channel8 UART0 rx */
+ <0x5a290000 0x10000>, /* channel9 UART0 tx */
+ <0x5a2a0000 0x10000>, /* channel10 UART1 rx */
+ <0x5a2b0000 0x10000>, /* channel11 UART1 tx */
+ <0x5a2c0000 0x10000>, /* channel12 UART2 rx */
+ <0x5a2d0000 0x10000>, /* channel13 UART2 tx */
+ <0x5a2e0000 0x10000>, /* channel14 UART3 rx */
+ <0x5a2f0000 0x10000>; /* channel15 UART3 tx */
+ #dma-cells = <3>;
+ dma-channels = <16>;
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma2-chan0-rx", "edma2-chan1-tx",
+ "edma2-chan2-rx", "edma2-chan3-tx",
+ "edma2-chan4-rx", "edma2-chan5-tx",
+ "edma2-chan6-rx", "edma2-chan7-tx",
+ "edma2-chan8-rx", "edma2-chan9-tx",
+ "edma2-chan10-rx", "edma2-chan11-tx",
+ "edma2-chan12-rx", "edma2-chan13-tx",
+ "edma2-chan14-rx", "edma2-chan15-tx";
+ power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
+ <&pd IMX_SC_R_DMA_2_CH1>,
+ <&pd IMX_SC_R_DMA_2_CH2>,
+ <&pd IMX_SC_R_DMA_2_CH3>,
+ <&pd IMX_SC_R_DMA_2_CH4>,
+ <&pd IMX_SC_R_DMA_2_CH5>,
+ <&pd IMX_SC_R_DMA_2_CH6>,
+ <&pd IMX_SC_R_DMA_2_CH7>,
+ <&pd IMX_SC_R_DMA_2_CH8>,
+ <&pd IMX_SC_R_DMA_2_CH9>,
+ <&pd IMX_SC_R_DMA_2_CH10>,
+ <&pd IMX_SC_R_DMA_2_CH11>,
+ <&pd IMX_SC_R_DMA_2_CH12>,
+ <&pd IMX_SC_R_DMA_2_CH13>,
+ <&pd IMX_SC_R_DMA_2_CH14>,
+ <&pd IMX_SC_R_DMA_2_CH15>;
+ power-domain-names = "edma2-chan0", "edma2-chan1",
+ "edma2-chan2", "edma2-chan3",
+ "edma2-chan4", "edma2-chan5",
+ "edma2-chan6", "edma2-chan7",
+ "edma2-chan8", "edma2-chan9",
+ "edma2-chan10", "edma2-chan11",
+ "edma2-chan12", "edma2-chan13",
+ "edma2-chan14", "edma2-chan15";
+ status = "disabled";
+ };
+
+ spi0_lpcg: clock-controller@5a400000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a400000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "spi0_lpcg_clk",
+ "spi0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_0>;
+ };
+
+ spi1_lpcg: clock-controller@5a410000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "spi1_lpcg_clk",
+ "spi1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_1>;
+ };
+
+ spi2_lpcg: clock-controller@5a420000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a420000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "spi2_lpcg_clk",
+ "spi2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_2>;
+ };
+
+ spi3_lpcg: clock-controller@5a430000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a430000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "spi3_lpcg_clk",
+ "spi3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_3>;
+ };
+
+ uart0_lpcg: clock-controller@5a460000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a460000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "uart0_lpcg_baud_clk",
+ "uart0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_0>;
+ };
+
+ uart1_lpcg: clock-controller@5a470000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a470000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "uart1_lpcg_baud_clk",
+ "uart1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_1>;
+ };
+
+ uart2_lpcg: clock-controller@5a480000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a480000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "uart2_lpcg_baud_clk",
+ "uart2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_2>;
+ };
+
+ uart3_lpcg: clock-controller@5a490000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a490000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "uart3_lpcg_baud_clk",
+ "uart3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_3>;
+ };
+
+ emvsim0_lpcg: clock-controller@5a4d0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a4d0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_EMVSIM_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "emvsim0_lpcg_clk",
+ "emvsim0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_EMVSIM_0>;
+ };
+
+ adc0: adc@5a880000 {
+ compatible = "fsl,imx8qxp-adc";
+ reg = <0x5a880000 0x10000>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adc0_lpcg 0>,
+ <&adc0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_ADC_0>;
+ status = "disabled";
+ };
+
+ adc1: adc@5a890000 {
+ compatible = "fsl,imx8qxp-adc";
+ reg = <0x5a890000 0x10000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adc1_lpcg 0>,
+ <&adc1_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_ADC_1>;
+ status = "disabled";
+ };
+
+
+ i2c0: i2c@5a800000 {
+ reg = <0x5a800000 0x4000>;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&i2c0_lpcg 0>,
+ <&i2c0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@5a810000 {
+ reg = <0x5a810000 0x4000>;
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&i2c1_lpcg 0>,
+ <&i2c1_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@5a820000 {
+ reg = <0x5a820000 0x4000>;
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&i2c2_lpcg 0>,
+ <&i2c2_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@5a830000 {
+ reg = <0x5a830000 0x4000>;
+ interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&i2c3_lpcg 0>,
+ <&i2c3_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_3>;
+ status = "disabled";
+ };
+
+ flexcan1: can@5a8d0000 {
+ compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+ reg = <0x5a8d0000 0x10000>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&can0_lpcg 1>,
+ <&can0_lpcg 0>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&pd IMX_SC_R_CAN_0>;
+ /* SLSlice[4] */
+ fsl,clk-source= <0>;
+ status = "disabled";
+ };
+
+ flexcan2: can@5a8e0000 {
+ compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+ reg = <0x5a8e0000 0x10000>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ /* CAN0 clock and PD is shared among all CAN instances as
+ * CAN1 shares CAN0's clock and to enable CAN0's clock it
+ * has to be powered on.
+ */
+ clocks = <&can0_lpcg 1>,
+ <&can0_lpcg 0>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&pd IMX_SC_R_CAN_1>;
+ /* SLSlice[4] */
+ fsl,clk-source = <0>;
+ status = "disabled";
+ };
+
+ flexcan3: can@5a8f0000 {
+ compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+ reg = <0x5a8f0000 0x10000>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ /* CAN0 clock and PD is shared among all CAN instances as
+ * CAN2 shares CAN0's clock and to enable CAN0's clock it
+ * has to be powered on.
+ */
+ clocks = <&can0_lpcg 1>,
+ <&can0_lpcg 0>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&pd IMX_SC_R_CAN_2>;
+ /* SLSlice[4] */
+ fsl,clk-source = <0>;
+ status = "disabled";
+ };
+
+ adc0_lpcg: clock-controller@5ac80000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac80000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "adc0_lpcg_clk",
+ "adc0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ADC_0>;
+ };
+
+ adc1_lpcg: clock-controller@5ac90000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac90000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "adc1_lpcg_clk",
+ "adc1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ADC_1>;
+ };
+
+ i2c0_lpcg: clock-controller@5ac00000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac00000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "i2c0_lpcg_clk",
+ "i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_0>;
+ };
+
+ i2c1_lpcg: clock-controller@5ac10000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac10000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "i2c1_lpcg_clk",
+ "i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_1>;
+ };
+
+ i2c2_lpcg: clock-controller@5ac20000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "i2c2_lpcg_clk",
+ "i2c2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_2>;
+ };
+
+ i2c3_lpcg: clock-controller@5ac30000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac30000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "i2c3_lpcg_clk",
+ "i2c3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_3>;
+ };
+
+ can0_lpcg: clock-controller@5acd0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5acd0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>, <&dma_ipg_clk>;
+ bit-offset = <0 16 20>;
+ clock-output-names = "can0_lpcg_pe_clk",
+ "can0_lpcg_ipg_clk",
+ "can0_lpcg_chi_clk";
+ power-domains = <&pd IMX_SC_R_CAN_0>;
+ };
+
+ i2c_rpbus_0: i2c-rpbus-0 {
+ compatible = "fsl,i2c-rpbus";
+ status = "disabled";
+ };
+
+ i2c_rpbus_1: i2c-rpbus-1 {
+ compatible = "fsl,i2c-rpbus";
+ status = "disabled";
+ };
+
+ i2c_rpbus_5: i2c-rpbus-5 {
+ compatible = "fsl,i2c-rpbus";
+ status = "disabled";
+ };
+
+ i2c_rpbus_12: i2c-rpbus-12 {
+ compatible = "fsl,i2c-rpbus";
+ status = "disabled";
+ };
+
+ i2c_rpbus_13: i2c-rpbus-13 {
+ compatible = "fsl,i2c-rpbus";
+ status = "disabled";
+ };
+
+ i2c_rpbus_14: i2c-rpbus-14 {
+ compatible = "fsl,i2c-rpbus";
+ status = "disabled";
+ };
+
+ i2c_rpbus_15: i2c-rpbus-15 {
+ compatible = "fsl,i2c-rpbus";
+ status = "disabled";
+ };
+
+ adma_pwm: pwm@5a190000 {
+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+ reg = <0x5a190000 0x1000>;
+ clocks = <&adma_pwm_lpcg 0>, <&adma_pwm_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <2>;
+ power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
+ status = "disabled";
+ };
+
+ adma_pwm_lpcg: clock-controller@5a590000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a590000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "adma_pwm_lpcg_clk",
+ "adma_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-gpu0.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-gpu0.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..28aeeecb1832399d9312586e52501e08d38c907c
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-gpu0.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+gpu0_subsys: bus@53100000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x53100000 0x0 0x53100000 0x40000>,
+ <0x80000000 0x0 0x80000000 0x80000000>,
+ <0x0 0x0 0x0 0x10000000>;
+
+ gpu_3d0: gpu@53100000 {
+ compatible = "fsl,imx8-gpu";
+ reg = <0x53100000 0x40000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
+ clock-names = "core", "shader";
+ assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
+ assigned-clock-rates = <700000000>, <850000000>;
+ power-domains = <&pd IMX_SC_R_GPU_0_PID0>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-gpu1.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-gpu1.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..0e84e5199a8f44277db89be357da5c6afe6de182
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-gpu1.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+gpu1_subsys: bus@54100000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x54100000 0x0 0x54100000 0x40000>,
+ <0x80000000 0x0 0x80000000 0x80000000>,
+ <0x0 0x0 0x0 0x10000000>;
+
+ gpu_3d1: gpu@54100000 {
+ compatible = "fsl,imx8-gpu";
+ reg = <0x54100000 0x40000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_MISC>;
+ clock-names = "core", "shader";
+ assigned-clocks = <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_MISC>;
+ assigned-clock-rates = <800000000>, <1000000000>;
+ fsl,sc_gpu_pid = <IMX_SC_R_GPU_1_PID0>;
+ power-domains = <&pd IMX_SC_R_GPU_1_PID0>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-hsio.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..c6629e048777f0cfb4d5db1ce1820f2f8e6543cc
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-hsio.dtsi
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Richard Zhu <hongxing.zhu@nxp.com>
+ */
+#include <dt-bindings/soc/imx8_hsio.h>
+
+hsio_subsys: bus@5f000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* Only supports up to 32bits DMA, map all possible DDR as inbound ranges */
+ dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
+ ranges = <0x5f000000 0x0 0x5f000000 0x21000000>;
+
+ xtal100m: clock-xtal100m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "xtal_100MHz";
+ };
+
+ hsio_refa_clk: clock-hsio-refa {
+ compatible = "gpio-gate-clock";
+ clocks = <&xtal100m>;
+ #clock-cells = <0>;
+ enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>;
+ };
+
+ hsio_refb_clk: clock-hsio-refb {
+ compatible = "gpio-gate-clock";
+ clocks = <&xtal100m>;
+ #clock-cells = <0>;
+ enable-gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>;
+ };
+
+ hsio_axi_clk: clock-hsio-axi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ clock-output-names = "hsio_axi_clk";
+ };
+
+ hsio_per_clk: clock-hsio-per {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133333333>;
+ clock-output-names = "hsio_per_clk";
+ };
+
+ pcieb_lpcg: clock-controller@5f060000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f060000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>;
+ bit-offset = <16 20 24>;
+ clock-output-names = "hsio_pcieb_mstr_axi_clk",
+ "hsio_pcieb_slv_axi_clk",
+ "hsio_pcieb_dbi_axi_clk";
+ power-domains = <&pd IMX_SC_R_PCIE_B>;
+ };
+
+ phyx1_crr1_lpcg: clock-controller@5f0b0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f0b0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_per_clk>;
+ bit-offset = <16>;
+ clock-output-names = "hsio_phyx1_per_clk";
+ power-domains = <&pd IMX_SC_R_SERDES_1>;
+ };
+
+ pcieb_crr3_lpcg: clock-controller@5f0d0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f0d0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_per_clk>;
+ bit-offset = <16>;
+ clock-output-names = "hsio_pcieb_per_clk";
+ power-domains = <&pd IMX_SC_R_PCIE_B>;
+ };
+
+ misc_crr5_lpcg: clock-controller@5f0f0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f0f0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_per_clk>;
+ bit-offset = <16>;
+ clock-output-names = "hsio_misc_per_clk";
+ power-domains = <&pd IMX_SC_R_HSIO_GPIO>;
+ };
+
+ pcieb: pcie@0x5f010000 {
+ compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
+ reg = <0x5f010000 0x10000>, /* Controller reg */
+ <0x7ff00000 0x80000>, /* PCI cfg space */
+ <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */
+ reg-names = "dbi", "config", "hsio";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x00000000 0x7ff80000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x70000000 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ num-viewport = <4>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+ interrupt-names = "msi", "dma";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic 0 105 4>,
+ <0 0 0 2 &gic 0 106 4>,
+ <0 0 0 3 &gic 0 107 4>,
+ <0 0 0 4 &gic 0 108 4>;
+ clocks = <&pcieb_lpcg 0>,
+ <&pcieb_lpcg 1>,
+ <&pcieb_lpcg 2>,
+ <&phyx1_lpcg 0>,
+ <&phyx1_crr1_lpcg 0>,
+ <&pcieb_crr3_lpcg 0>,
+ <&misc_crr5_lpcg 0>;
+ clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
+ "pcie_phy", "phy_per", "pcie_per", "misc_per";
+ power-domains = <&pd IMX_SC_R_PCIE_B>,
+ <&pd IMX_SC_R_SERDES_1>,
+ <&pd IMX_SC_R_HSIO_GPIO>;
+ power-domain-names = "pcie", "pcie_phy", "hsio_gpio";
+ fsl,max-link-speed = <3>;
+ hsio-cfg = <PCIEAX2PCIEBX1>;
+ local-addr = <0x80000000>;
+ status = "disabled";
+ };
+
+ pcieb_ep: pcie_ep@0x5f010000 {
+ compatible = "fsl,imx8qxp-pcie-ep";
+ reg = <0x5f010000 0x00010000>,
+ <0x5f080000 0xf0000>, /* lpcg, csr, msic, gpio */
+ <0x70000000 0x10000000>;
+ reg-names = "regs", "hsio", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+ interrupt-names = "dma";
+ clocks = <&pcieb_lpcg 0>,
+ <&pcieb_lpcg 1>,
+ <&pcieb_lpcg 2>,
+ <&phyx1_lpcg 0>,
+ <&phyx1_crr1_lpcg 0>,
+ <&pcieb_crr3_lpcg 0>,
+ <&misc_crr5_lpcg 0>;
+ clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
+ "pcie_phy", "phy_per", "pcie_per", "misc_per";
+ power-domains = <&pd IMX_SC_R_PCIE_B>,
+ <&pd IMX_SC_R_SERDES_1>,
+ <&pd IMX_SC_R_HSIO_GPIO>;
+ power-domain-names = "pcie", "pcie_phy", "hsio_gpio";
+ fsl,max-link-speed = <3>;
+ hsio-cfg = <PCIEAX2PCIEBX1>;
+ local-addr = <0x80000000>;
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-img.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-img.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..8962390ed4aa3a1b1311ed0c7075285a14221e58
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-img.dtsi
@@ -0,0 +1,604 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2020 NXP
+ * Zhou Guoniu <guoniu.zhou@nxp.com>
+ */
+img_subsys: bus@58000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x58000000 0x0 0x58000000 0x1000000>;
+
+ img_ipg_clk: clock-img-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "img_ipg_clk";
+ };
+
+ img_axi_clk: clock-img-axi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ clock-output-names = "img_axi_clk";
+ };
+
+ img_pxl_clk: clock-img-pxl {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <600000000>;
+ clock-output-names = "img_pxl_clk";
+ };
+
+ csi0_core_lpcg: clock-controller@58223018 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58223018 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER>;
+ bit-offset = <16>;
+ clock-output-names = "csi0_lpcg_core_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH0>;
+ };
+
+ csi0_esc_lpcg: clock-controller@5822301c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5822301c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC>;
+ bit-offset = <16>;
+ clock-output-names = "csi0_lpcg_esc_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH0>;
+ };
+
+ csi1_core_lpcg: clock-controller@58243018 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58243018 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER>;
+ bit-offset = <16>;
+ clock-output-names = "csi1_lpcg_core_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH0>;
+ };
+
+ csi1_esc_lpcg: clock-controller@5824301c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5824301c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC>;
+ bit-offset = <16>;
+ clock-output-names = "csi1_lpcg_esc_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH0>;
+ };
+
+ pi0_pxl_lpcg: clock-controller@58263018 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58263018 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
+ bit-offset = <0>;
+ clock-output-names = "pi0_lpcg_pxl_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH0>;
+ };
+
+ pi0_ipg_lpcg: clock-controller@58263004 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58263004 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
+ bit-offset = <16>;
+ clock-output-names = "pi0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH0>;
+ };
+
+ pi0_misc_lpcg: clock-controller@5826301c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5826301c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0>;
+ bit-offset = <0>;
+ clock-output-names = "pi0_lpcg_misc_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH0>;
+ };
+
+ pdma0_lpcg: clock-controller@58500000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58500000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&img_pxl_clk>;
+ bit-offset = <0>;
+ clock-output-names = "pdma0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH0>;
+ };
+
+ pdma1_lpcg: clock-controller@58510000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58510000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&img_pxl_clk>;
+ bit-offset = <0>;
+ clock-output-names = "pdma1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH1>;
+ };
+
+ pdma2_lpcg: clock-controller@58520000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58520000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&img_pxl_clk>;
+ bit-offset = <0>;
+ clock-output-names = "pdma2_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH2>;
+ };
+
+ pdma3_lpcg: clock-controller@58530000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58530000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&img_pxl_clk>;
+ bit-offset = <0>;
+ clock-output-names = "pdma3_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH3>;
+ };
+
+ pdma4_lpcg: clock-controller@58540000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58540000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&img_pxl_clk>;
+ bit-offset = <0>;
+ clock-output-names = "pdma4_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH4>;
+ };
+
+ pdma5_lpcg: clock-controller@58550000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58550000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&img_pxl_clk>;
+ bit-offset = <0>;
+ clock-output-names = "pdma5_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH5>;
+ };
+
+ pdma6_lpcg: clock-controller@58560000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58560000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&img_pxl_clk>;
+ bit-offset = <0>;
+ clock-output-names = "pdma6_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH6>;
+ };
+
+ pdma7_lpcg: clock-controller@58570000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58570000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&img_pxl_clk>;
+ bit-offset = <0>;
+ clock-output-names = "pdma7_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_ISI_CH7>;
+ };
+
+ csi0_pxl_lpcg: clock-controller@58580000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58580000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&img_pxl_clk>;
+ bit-offset = <0>;
+ clock-output-names = "csi0_lpcg_pxl_clk";
+ power-domains = <&pd IMX_SC_R_CSI_0>;
+ };
+
+ csi1_pxl_lpcg: clock-controller@58590000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58590000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&img_pxl_clk>;
+ bit-offset = <0>;
+ clock-output-names = "csi1_lpcg_pxl_clk";
+ power-domains = <&pd IMX_SC_R_CSI_1>;
+ };
+
+ hdmi_rx_pxl_link_lpcg: clock-controller@585a0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x585a0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&img_pxl_clk>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_rx_lpcg_pxl_link_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX>;
+ };
+
+ img_jpeg_dec_clk: clock-controller@585d0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x585d0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&img_ipg_clk>, <&img_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "img_jpeg_dec_clk",
+ "img_jpeg_dec_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
+ };
+
+ img_jpeg_enc_clk: clock-controller@585f0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x585f0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&img_ipg_clk>, <&img_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "img_jpeg_enc_clk",
+ "img_jpeg_enc_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
+ };
+
+ irqsteer_csi0: irqsteer@58220000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x58220000 0x1000>;
+ interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ clocks = <&img_ipg_clk>;
+ clock-names = "ipg";
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>;
+ power-domain-names = "pd_csi", "pd_isi_ch0";
+ status = "disabled";
+ };
+
+ irqsteer_csi1: irqsteer@58240000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x58240000 0x1000>;
+ interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ clocks = <&img_ipg_clk>;
+ clock-names = "ipg";
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>;
+ power-domain-names = "pd_csi", "pd_isi_ch0";
+ status = "disabled";
+ };
+
+ irqsteer_parallel: irqsteer@58260000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x58260000 0x1000>;
+ interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ clocks = <&clk_dummy>;
+ clock-names = "ipg";
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>;
+ power-domain-names = "pd_pi", "pd_isi_ch0";
+ status = "disabled";
+ };
+
+ gpio0_mipi_csi0: gpio@58222000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x58222000 0x1000>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&irqsteer_csi0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>;
+ power-domain-names = "pd_csi", "pd_isi_ch0";
+ };
+
+ i2c_mipi_csi0: i2c@58226000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x58226000 0x1000>;
+ interrupts = <8>;
+ interrupt-parent = <&irqsteer_csi0>;
+ clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&img_ipg_clk>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_CSI_0_I2C_0>;
+ status = "disabled";
+ };
+
+ i2c0_parallel: i2c@58266000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x58266000 0x1000>;
+ interrupts = <8>;
+ interrupt-parent = <&irqsteer_parallel>;
+ clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&img_ipg_clk>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_PI_0_I2C_0>;
+ status = "disabled";
+ };
+
+ gpio0_mipi_csi1: gpio@58242000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x58242000 0x1000>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&irqsteer_csi1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>;
+ power-domain-names = "pd_csi", "pd_isi_ch0";
+ };
+
+ i2c_mipi_csi1: i2c@58246000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x58246000 0x1000>;
+ interrupts = <8>;
+ interrupt-parent = <&irqsteer_csi1>;
+ clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&img_ipg_clk>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_CSI_1_I2C_0>;
+ status = "disabled";
+ };
+
+ cameradev: camera {
+ compatible = "fsl,mxc-md", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ isi_0: isi@58100000 {
+ compatible = "fsl,imx8-isi";
+ reg = <0x58100000 0x10000>;
+ interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&pdma0_lpcg 0>;
+ clock-names = "per";
+ power-domains = <&pd IMX_SC_R_ISI_CH0>;
+ interface = <2 0 2>;
+ no-reset-control;
+ status = "disabled";
+
+ cap_device {
+ compatible = "imx-isi-capture";
+ status = "disabled";
+ };
+
+ m2m_device{
+ compatible = "imx-isi-m2m";
+ status = "disabled";
+ };
+ };
+
+ isi_1: isi@58110000 {
+ compatible = "fsl,imx8-isi";
+ reg = <0x58110000 0x10000>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&pdma1_lpcg 0>;
+ clock-names = "per";
+ power-domains = <&pd IMX_SC_R_ISI_CH1>;
+ interface = <2 1 2>;
+ no-reset-control;
+ status = "disabled";
+
+ cap_device {
+ compatible = "imx-isi-capture";
+ status = "disabled";
+ };
+ };
+
+ isi_2: isi@58120000 {
+ compatible = "fsl,imx8-isi";
+ reg = <0x58120000 0x10000>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&pdma2_lpcg 0>;
+ clock-names = "per";
+ power-domains = <&pd IMX_SC_R_ISI_CH2>;
+ interface = <2 2 2>;
+ no-reset-control;
+ status = "disabled";
+
+ cap_device {
+ compatible = "imx-isi-capture";
+ status = "disabled";
+ };
+ };
+
+ isi_3: isi@58130000 {
+ compatible = "fsl,imx8-isi";
+ reg = <0x58130000 0x10000>;
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&pdma3_lpcg 0>;
+ clock-names = "per";
+ power-domains = <&pd IMX_SC_R_ISI_CH3>;
+ interface = <2 3 2>;
+ no-reset-control;
+ status = "disabled";
+
+ cap_device {
+ compatible = "imx-isi-capture";
+ status = "disabled";
+ };
+ };
+
+ isi_4: isi@58140000 {
+ compatible = "fsl,imx8-isi";
+ reg = <0x58140000 0x10000>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&pdma4_lpcg 0>;
+ clock-names = "per";
+ power-domains = <&pd IMX_SC_R_ISI_CH4>;
+ interface = <3 0 2>;
+ no-reset-control;
+ status = "disabled";
+
+ cap_device {
+ compatible = "imx-isi-capture";
+ status = "disabled";
+ };
+ };
+
+ isi_5: isi@58150000 {
+ compatible = "fsl,imx8-isi";
+ reg = <0x58150000 0x10000>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&pdma5_lpcg 0>;
+ clock-names = "per";
+ power-domains = <&pd IMX_SC_R_ISI_CH5>;
+ interface = <3 1 2>;
+ no-reset-control;
+ status = "disabled";
+
+ cap_device {
+ compatible = "imx-isi-capture";
+ status = "disabled";
+ };
+ };
+
+ isi_6: isi@58160000 {
+ compatible = "fsl,imx8-isi";
+ reg = <0x58160000 0x10000>;
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&pdma6_lpcg 0>;
+ clock-names = "per";
+ power-domains = <&pd IMX_SC_R_ISI_CH6>;
+ interface = <3 2 2>;
+ no-reset-control;
+ status = "disabled";
+
+ cap_device {
+ compatible = "imx-isi-capture";
+ status = "disabled";
+ };
+ };
+
+ isi_7: isi@58170000 {
+ compatible = "fsl,imx8-isi";
+ reg = <0x58170000 0x10000>;
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&pdma7_lpcg 0>;
+ clock-names = "per";
+ power-domains = <&pd IMX_SC_R_ISI_CH7>;
+ interface = <3 3 2>;
+ no-reset-control;
+ status = "disabled";
+
+ cap_device {
+ compatible = "imx-isi-capture";
+ status = "disabled";
+ };
+ };
+
+ mipi_csi_0: csi@58227000 {
+ compatible = "fsl,mxc-mipi-csi2";
+ reg = <0x58227000 0x1000>,
+ <0x58221000 0x1000>;
+ clocks = <&csi0_core_lpcg 0>,
+ <&csi0_esc_lpcg 0>,
+ <&csi0_pxl_lpcg 0>;
+ clock-names = "clk_core", "clk_esc", "clk_pxl";
+ assigned-clocks = <&csi0_core_lpcg 0>,
+ <&csi0_esc_lpcg 0>;
+ assigned-clock-rates = <360000000>, <72000000>;
+ power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>;
+ power-domain-names = "pd_csi", "pd_isi_ch0";
+ status = "disabled";
+ };
+
+ mipi_csi_1: csi@58247000{
+ compatible = "fsl,mxc-mipi-csi2";
+ reg = <0x58247000 0x1000>,
+ <0x58241000 0x1000>;
+ clocks = <&csi1_core_lpcg 0>,
+ <&csi1_esc_lpcg 0>,
+ <&csi1_pxl_lpcg 0>;
+ clock-names = "clk_core", "clk_esc", "clk_pxl";
+ assigned-clocks = <&csi1_core_lpcg 0>,
+ <&csi1_esc_lpcg 0>;
+ assigned-clock-rates = <360000000>, <72000000>;
+ power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>;
+ power-domain-names = "pd_csi", "pd_isi_ch0";
+ status = "disabled";
+ };
+
+ parallel_csi: pcsi@58261000 {
+ compatible = "fsl,mxc-parallel-csi";
+ reg = <0x58261000 0x1000>;
+ clocks = <&pi0_pxl_lpcg 0>,
+ <&pi0_ipg_lpcg 0>,
+ <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>;
+ clock-names = "pixel", "ipg", "div", "dpll";
+ assigned-clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-parents = <&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>;
+ assigned-clock-rates = <160000000>; /* 160MHz */
+ power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>;
+ power-domain-names = "pd_pi", "pd_isi_ch0";
+ status = "disabled";
+ };
+
+ jpegdec: jpegdec@58400000 {
+ compatible = "fsl,imx8-jpgdec";
+ reg = <0x58400000 0x00050000 >;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&img_jpeg_dec_clk 0>,
+ <&img_jpeg_dec_clk 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&img_jpeg_dec_clk 0>,
+ <&img_jpeg_dec_clk 1>;
+ assigned-clock-rates = <200000000>;
+ power-domains = <&pd IMX_SC_R_ISI_CH0>,
+ <&pd IMX_SC_R_MJPEG_DEC_MP>,
+ <&pd IMX_SC_R_MJPEG_DEC_S0>,
+ <&pd IMX_SC_R_MJPEG_DEC_S1>,
+ <&pd IMX_SC_R_MJPEG_DEC_S2>,
+ <&pd IMX_SC_R_MJPEG_DEC_S3>;
+ power-domain-names = "pd_isi_ch0", "pd_dec_mp",
+ "pd_dec_s0", "pd_dec_s1",
+ "pd_dec_s2", "pd_dec_s3";
+ status = "disabled";
+ };
+
+ jpegenc: jpegenc@58450000 {
+ compatible = "fsl,imx8-jpgenc";
+ reg = <0x58450000 0x00050000 >;
+ interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&img_jpeg_enc_clk 0>,
+ <&img_jpeg_enc_clk 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&img_jpeg_enc_clk 0>,
+ <&img_jpeg_enc_clk 1>;
+ assigned-clock-rates = <200000000>;
+ power-domains = <&pd IMX_SC_R_ISI_CH0>,
+ <&pd IMX_SC_R_MJPEG_ENC_MP>,
+ <&pd IMX_SC_R_MJPEG_ENC_S0>,
+ <&pd IMX_SC_R_MJPEG_ENC_S1>,
+ <&pd IMX_SC_R_MJPEG_ENC_S2>,
+ <&pd IMX_SC_R_MJPEG_ENC_S3>;
+ power-domain-names = "pd_isi_ch0", "pd_enc_mp",
+ "pd_enc_s0", "pd_enc_s1",
+ "pd_enc_s2", "pd_enc_s3";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-lcdif.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-lcdif.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..4bf058106fecf630c44e7e68dba2cd0b9683df34
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-lcdif.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+lcdif_subsys: bus@5a180000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5a180000 0x0 0x5a180000 0x500000>;
+
+ ipg_dma_clk: clock-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <120000000>;
+ clock-output-names = "ipg_dma_clk";
+ };
+
+ lcd_clk_lpcg: clock-controller@5a580000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a580000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>,
+ <&ipg_dma_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "lcd_clk_lpcg", "lcd_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LCD_0>;
+ };
+
+ adma_lcdif: lcdif@5a180000 {
+ compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif";
+ reg = <0x5a180000 0x10000>;
+ clocks = <&lcd_clk_lpcg 0>,
+ <&lcd_clk_lpcg 1>,
+ <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
+ clock-names = "pix", "axi", "disp_axi";
+ assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>,
+ <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>;
+ assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>;
+ assigned-clock-rates = <0>, <24000000>, <804000000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd IMX_SC_R_LCD_0>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-lsio.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..f406f6adce31bac5b1297ac501f1c80bdf3a4f75
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-lsio.dtsi
@@ -0,0 +1,319 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+lsio_subsys: bus@5d000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5d000000 0x0 0x5d000000 0x1000000>,
+ <0x08000000 0x0 0x08000000 0x10000000>;
+
+ lsio_mem_clk: clock-lsio-mem {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lsio_mem_clk";
+ };
+
+ lsio_bus_clk: clock-lsio-bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "lsio_bus_clk";
+ };
+
+ lsio_gpio0: gpio@5d080000 {
+ reg = <0x5d080000 0x10000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_0>;
+ };
+
+ lsio_gpio1: gpio@5d090000 {
+ reg = <0x5d090000 0x10000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_1>;
+ };
+
+ lsio_gpio2: gpio@5d0a0000 {
+ reg = <0x5d0a0000 0x10000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_2>;
+ };
+
+ lsio_gpio3: gpio@5d0b0000 {
+ reg = <0x5d0b0000 0x10000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_3>;
+ };
+
+ lsio_gpio4: gpio@5d0c0000 {
+ reg = <0x5d0c0000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_4>;
+ };
+
+ lsio_gpio5: gpio@5d0d0000 {
+ reg = <0x5d0d0000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_5>;
+ };
+
+ lsio_gpio6: gpio@5d0e0000 {
+ reg = <0x5d0e0000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_6>;
+ };
+
+ lsio_gpio7: gpio@5d0f0000 {
+ reg = <0x5d0f0000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_7>;
+ };
+
+ flexspi0: spi@5d120000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imx8qxp-fspi";
+ reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>;
+ clock-names = "fspi", "fspi_en";
+ power-domains = <&pd IMX_SC_R_FSPI_0>;
+ status = "disabled";
+ };
+
+ lsio_mu0: mailbox@5d1b0000 {
+ reg = <0x5d1b0000 0x10000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ lsio_mu1: mailbox@5d1c0000 {
+ reg = <0x5d1c0000 0x10000>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ lsio_mu2: mailbox@5d1d0000 {
+ reg = <0x5d1d0000 0x10000>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ lsio_mu3: mailbox@5d1e0000 {
+ reg = <0x5d1e0000 0x10000>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ lsio_mu4: mailbox@5d1f0000 {
+ reg = <0x5d1f0000 0x10000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ lsio_mu5: mailbox@5d200000 {
+ compatible = "fsl,imx6sx-mu";
+ reg = <0x5d200000 0x10000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_MU_5A>;
+ };
+
+ lsio_mu13: mailbox@5d280000 {
+ compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu";
+ reg = <0x5d280000 0x10000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_MU_13A>;
+ fsl,dsp_ap_mu_id = <13>;
+ };
+
+ /* LPCG clocks */
+ pwm0_lpcg: clock-controller@5d400000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5d400000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm0_lpcg_ipg_clk",
+ "pwm0_lpcg_ipg_hf_clk",
+ "pwm0_lpcg_ipg_s_clk",
+ "pwm0_lpcg_ipg_slv_clk",
+ "pwm0_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_0>;
+ };
+
+ pwm1_lpcg: clock-controller@5d410000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5d410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm1_lpcg_ipg_clk",
+ "pwm1_lpcg_ipg_hf_clk",
+ "pwm1_lpcg_ipg_s_clk",
+ "pwm1_lpcg_ipg_slv_clk",
+ "pwm1_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_1>;
+ };
+
+ pwm2_lpcg: clock-controller@5d420000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5d420000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm2_lpcg_ipg_clk",
+ "pwm2_lpcg_ipg_hf_clk",
+ "pwm2_lpcg_ipg_s_clk",
+ "pwm2_lpcg_ipg_slv_clk",
+ "pwm2_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_2>;
+ };
+
+ pwm3_lpcg: clock-controller@5d430000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5d430000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm3_lpcg_ipg_clk",
+ "pwm3_lpcg_ipg_hf_clk",
+ "pwm3_lpcg_ipg_s_clk",
+ "pwm3_lpcg_ipg_slv_clk",
+ "pwm3_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_3>;
+ };
+
+ pwm4_lpcg: clock-controller@5d440000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5d440000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm4_lpcg_ipg_clk",
+ "pwm4_lpcg_ipg_hf_clk",
+ "pwm4_lpcg_ipg_s_clk",
+ "pwm4_lpcg_ipg_slv_clk",
+ "pwm4_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_4>;
+ };
+
+ pwm5_lpcg: clock-controller@5d450000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5d450000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm5_lpcg_ipg_clk",
+ "pwm5_lpcg_ipg_hf_clk",
+ "pwm5_lpcg_ipg_s_clk",
+ "pwm5_lpcg_ipg_slv_clk",
+ "pwm5_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_5>;
+ };
+
+ pwm6_lpcg: clock-controller@5d460000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5d460000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm6_lpcg_ipg_clk",
+ "pwm6_lpcg_ipg_hf_clk",
+ "pwm6_lpcg_ipg_s_clk",
+ "pwm6_lpcg_ipg_slv_clk",
+ "pwm6_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_6>;
+ };
+
+ pwm7_lpcg: clock-controller@5d470000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5d470000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
+ bit-offset = <0 4 16 20 24>;
+ clock-output-names = "pwm7_lpcg_ipg_clk",
+ "pwm7_lpcg_ipg_hf_clk",
+ "pwm7_lpcg_ipg_s_clk",
+ "pwm7_lpcg_ipg_slv_clk",
+ "pwm7_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_7>;
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-security.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-security.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..57734ed8a9226a48d94096d5769e24f043843793
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-security.dtsi
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+security_subsys: bus@31400000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x31400000 0x0 0x31400000 0x410000>;
+
+ crypto: crypto@31400000 {
+ compatible = "fsl,sec-v4.0";
+ reg = <0x31400000 0x90000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x31400000 0x90000>;
+ fsl,sec-era = <9>;
+ power-domains = <&pd IMX_SC_R_CAAM_JR2>;
+ power-domain-names = "jr";
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd IMX_SC_R_CAAM_JR2>;
+ power-domain-names = "jr";
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd IMX_SC_R_CAAM_JR3>;
+ power-domain-names = "jr";
+ };
+ };
+
+ caam_sm: caam-sm@31800000 {
+ compatible = "fsl,imx6q-caam-sm";
+ reg = <0x31800000 0x10000>;
+ };
+
+ sec_mu2: mu@31560000 {
+ compatible = "fsl,imx8-mu-seco";
+ reg = <0x31560000 0x10000>;
+ interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_SECO_MU_2>;
+ status = "okay";
+ };
+
+ sec_mu3: mu@31570000 {
+ compatible = "fsl,imx8-mu-seco";
+ reg = <0x31570000 0x10000>;
+ interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_SECO_MU_3>;
+ status = "okay";
+ };
+
+ sec_mu4: mu@31580000 {
+ compatible = "fsl,imx8-mu-seco";
+ reg = <0x31580000 0x10000>;
+ interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_SECO_MU_4>;
+ status = "okay";
+ };
+};
+
+seco_mu1: seco_mu1 {
+ compatible = "fsl,imx-seco-mu";
+ mbox-names = "txdb", "rxdb";
+ mboxes = <&sec_mu2 2 0
+ &sec_mu2 3 0>;
+
+ fsl,seco_mu_id = <1>;
+ fsl,seco_max_users = <4>;
+ status = "okay";
+};
+
+seco_mu2: seco_mu2 {
+ compatible = "fsl,imx-seco-mu";
+ mbox-names = "txdb", "rxdb";
+ mboxes = <&sec_mu3 2 0
+ &sec_mu3 3 0>;
+
+ fsl,seco_mu_id = <2>;
+ fsl,seco_max_users = <4>;
+ status = "okay";
+};
+
+seco_mu3: seco_mu3 {
+ compatible = "fsl,imx-seco-mu";
+ mbox-names = "txdb", "rxdb";
+ mboxes = <&sec_mu4 2 0
+ &sec_mu4 3 0>;
+
+ fsl,seco_mu_id = <3>;
+ fsl,seco_max_users = <4>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-v2x.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-v2x.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..5ee8c6a2615a17811ba049834b52768e1771887d
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-v2x.dtsi
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+v2x_subsys: bus@2C000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x2c000000 0x0 0x2c000000 0x50000>;
+
+ v2x_sv0: mu@2C000000 {
+ compatible = "fsl,imx8-mu-seco";
+ reg = <0x2c000000 0x10000>;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_V2X_MU_0>;
+ status = "okay";
+ };
+ v2x_sv1: mu@2c010000 {
+ compatible = "fsl,imx8-mu-seco";
+ reg = <0x2c010000 0x10000>;
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_V2X_MU_1>;
+ status = "okay";
+ };
+ v2x_she: mu@2c020000 {
+ compatible = "fsl,imx8-mu-seco";
+ reg = <0x2c020000 0x10000>;
+ interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_V2X_MU_2>;
+ status = "okay";
+ };
+ v2x_sg0: mu@2c030000 {
+ compatible = "fsl,imx8-mu-seco";
+ reg = <0x2c030000 0x10000>;
+ interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_V2X_MU_3>;
+ status = "okay";
+ };
+ v2x_sg1: mu@2c040000 {
+ compatible = "fsl,imx8-mu-seco";
+ reg = <0x2c040000 0x10000>;
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_V2X_MU_4>;
+ status = "okay";
+ };
+};
+
+v2x_mu_sv0: v2x_mu_sv0 {
+ compatible = "fsl,imx-seco-mu";
+ mbox-names = "txdb", "rxdb";
+ mboxes = <&v2x_sv0 2 0
+ &v2x_sv0 3 0>;
+
+ fsl,seco_mu_id = <4>;
+ fsl,seco_max_users = <2>;
+ fsl,cmd_tag = /bits/ 8 <0x18>;
+ fsl,rsp_tag = /bits/ 8 <0xe2>;
+ status = "okay";
+};
+v2x_mu_sv1: v2x_mu_sv1 {
+ compatible = "fsl,imx-seco-mu";
+ mbox-names = "txdb", "rxdb";
+ mboxes = <&v2x_sv1 2 0
+ &v2x_sv1 3 0>;
+
+ fsl,seco_mu_id = <5>;
+ fsl,seco_max_users = <2>;
+ fsl,cmd_tag = /bits/ 8 <0x19>;
+ fsl,rsp_tag = /bits/ 8 <0xe3>;
+ status = "okay";
+};
+v2x_mu_she: v2x_mu_she {
+ compatible = "fsl,imx-seco-mu";
+ mbox-names = "txdb", "rxdb";
+ mboxes = <&v2x_she 2 0
+ &v2x_she 3 0>;
+
+ fsl,seco_mu_id = <6>;
+ fsl,seco_max_users = <2>;
+ fsl,cmd_tag = /bits/ 8 <0x1a>;
+ fsl,rsp_tag = /bits/ 8 <0xe4>;
+ status = "okay";
+};
+v2x_mu_sg0: v2x_mu_sg0 {
+ compatible = "fsl,imx-seco-mu";
+ mbox-names = "txdb", "rxdb";
+ mboxes = <&v2x_sg0 2 0
+ &v2x_sg0 3 0>;
+
+ fsl,seco_mu_id = <7>;
+ fsl,seco_max_users = <2>;
+ fsl,cmd_tag = /bits/ 8 <0x1d>;
+ fsl,rsp_tag = /bits/ 8 <0xe7>;
+ status = "okay";
+};
+v2x_mu_sg1: v2x_mu_sg1 {
+ compatible = "fsl,imx-seco-mu";
+ mbox-names = "txdb", "rxdb";
+ mboxes = <&v2x_sg1 2 0
+ &v2x_sg1 3 0>;
+
+ fsl,seco_mu_id = <8>;
+ fsl,seco_max_users = <2>;
+ fsl,cmd_tag = /bits/ 8 <0x1e>;
+ fsl,rsp_tag = /bits/ 8 <0xe8>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/seco/include/imx8-ss-vpu.dtsi
new file mode 100755
index 0000000000000000000000000000000000000000..96787fb70221d98f2e04f386234cbf8bf506d44f
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8-ss-vpu.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+vpu_subsys: bus@2c000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
+
+ vpu_lpcg: clock-controller@2d000000 {
+ compatible = "fsl,imx8qxp-lpcg-vpu";
+ reg = <0x2c000000 0x2000000>;
+ #clock-cells = <1>;
+ status = "disabled";
+ };
+
+ vpu_decoder: vpu_decoder@2c000000 {
+ compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec";
+ reg = <0x2c000000 0x1000000>;
+ reg-names = "vpu_regs";
+ power-domains = <&pd IMX_SC_R_VPU_DEC_0>,
+ <&pd IMX_SC_R_VPU>;
+ power-domain-names = "vpudec", "vpu";
+
+ mbox-names = "tx0", "tx1", "rx";
+ mboxes = <&mu_m0 0 0
+ &mu_m0 0 1
+ &mu_m0 1 0>;
+
+ status = "disabled";
+ };
+
+ vpu_encoder: vpu_encoder@2d000000 {
+ compatible = "nxp,imx8qxp-b0-vpuenc";
+ reg = <0x2d000000 0x1000000>, /*VPU Encoder*/
+ <0x2c000000 0x2000000>; /*VPU*/
+ reg-names = "vpu_regs";
+ power-domains = <&pd IMX_SC_R_VPU_ENC_0>,
+ <&pd IMX_SC_R_VPU>;
+ power-domain-names = "vpuenc1", "vpu";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ };
+
+ mu_m0: mailbox@2d000000 {
+ compatible = "fsl,imx8-mu0-vpu-m0", "fsl,imx6sx-mu";
+ reg = <0x2d000000 0x20000>;
+ interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_VPU_MU_0>;
+ power-domain-names = "vpumu0";
+ fsl,vpu_ap_mu_id = <16>;
+ status = "okay";
+ };
+
+ mu1_m0: mailbox@2d020000 {
+ compatible = "fsl,imx8-mu1-vpu-m0", "fsl,imx6sx-mu";
+ reg = <0x2d020000 0x20000>;
+ interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,vpu_ap_mu_id = <17>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_VPU_MU_1>;
+ power-domain-names = "vpumu1";
+ status = "okay";
+ };
+
+ mu2_m0: mailbox@2d040000 {
+ compatible = "fsl,imx8-mu2-vpu-m0", "fsl,imx6sx-mu";
+ reg = <0x2d040000 0x20000>;
+ interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,vpu_ap_mu_id = <18>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_VPU_MU_2>;
+ power-domain-names = "vpumu2";
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qm-ss-audio.dtsi b/arch/arm64/boot/dts/seco/include/imx8qm-ss-audio.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..bdf0166fcb84decd91914bfb3b75c417d582e288
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qm-ss-audio.dtsi
@@ -0,0 +1,462 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+/delete-node/ &acm;
+/delete-node/ &sai4;
+/delete-node/ &sai5;
+/delete-node/ &sai4_lpcg;
+/delete-node/ &sai5_lpcg;
+
+/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */
+&edma0{
+ reg = <0x591f0000 0x10000>,
+ <0x59200000 0x10000>, /* asrc0 */
+ <0x59210000 0x10000>,
+ <0x59220000 0x10000>,
+ <0x59230000 0x10000>,
+ <0x59240000 0x10000>,
+ <0x59250000 0x10000>,
+ <0x59260000 0x10000>, /* esai0 rx */
+ <0x59270000 0x10000>, /* esai0 tx */
+ <0x59280000 0x10000>, /* spdif0 rx */
+ <0x59290000 0x10000>, /* spdif0 tx */
+ <0x592A0000 0x10000>, /* spdif1 rx */
+ <0x592B0000 0x10000>, /* spdif1 tx */
+ <0x592c0000 0x10000>, /* sai0 rx */
+ <0x592d0000 0x10000>, /* sai0 tx */
+ <0x592e0000 0x10000>, /* sai1 rx */
+ <0x592f0000 0x10000>, /* sai1 tx */
+ <0x59300000 0x10000>, /* sai2 rx */
+ <0x59310000 0x10000>, /* sai3 rx */
+ <0x59320000 0x10000>, /* sai4 rx */
+ <0x59330000 0x10000>; /* sai5 tx */
+ dma-channels = <20>;
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, /* spdif1 */
+ <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
+ interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */
+ "edma2-chan2-rx", "edma2-chan3-tx",
+ "edma2-chan4-tx", "edma2-chan5-tx",
+ "edma2-chan6-rx", "edma2-chan7-tx", /* esai0 */
+ "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */
+ "edma2-chan10-rx", "edma2-chan11-tx", /* spdif1 */
+ "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */
+ "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */
+ "edma2-chan16-rx", "edma2-chan17-tx", /* sai2, dai3 */
+ "edma2-chan18-rx", "edma2-chan19-tx"; /* sai4, sai5 */
+ power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
+ <&pd IMX_SC_R_DMA_2_CH1>,
+ <&pd IMX_SC_R_DMA_2_CH2>,
+ <&pd IMX_SC_R_DMA_2_CH3>,
+ <&pd IMX_SC_R_DMA_2_CH4>,
+ <&pd IMX_SC_R_DMA_2_CH5>,
+ <&pd IMX_SC_R_DMA_2_CH6>,
+ <&pd IMX_SC_R_DMA_2_CH7>,
+ <&pd IMX_SC_R_DMA_2_CH8>,
+ <&pd IMX_SC_R_DMA_2_CH9>,
+ <&pd IMX_SC_R_DMA_2_CH10>,
+ <&pd IMX_SC_R_DMA_2_CH11>,
+ <&pd IMX_SC_R_DMA_2_CH12>,
+ <&pd IMX_SC_R_DMA_2_CH13>,
+ <&pd IMX_SC_R_DMA_2_CH14>,
+ <&pd IMX_SC_R_DMA_2_CH15>,
+ <&pd IMX_SC_R_DMA_2_CH16>,
+ <&pd IMX_SC_R_DMA_2_CH17>,
+ <&pd IMX_SC_R_DMA_2_CH18>,
+ <&pd IMX_SC_R_DMA_2_CH19>;
+ power-domain-names = "edma2-chan0", "edma2-chan1",
+ "edma2-chan2", "edma2-chan3",
+ "edma2-chan4", "edma2-chan5",
+ "edma2-chan6", "edma2-chan7",
+ "edma2-chan8", "edma2-chan9",
+ "edma2-chan10", "edma2-chan11",
+ "edma2-chan12", "edma2-chan13",
+ "edma2-chan14", "edma2-chan15",
+ "edma2-chan16", "edma2-chan17",
+ "edma2-chan18", "edma2-chan19";
+};
+
+/* edma3 called in imx8qm RM with the same address in edma1 of imx8qxp */
+&edma1{
+ reg = <0x599F0000 0x10000>,
+ <0x59A00000 0x10000>, /* asrc1 */
+ <0x59A10000 0x10000>,
+ <0x59A20000 0x10000>,
+ <0x59A30000 0x10000>,
+ <0x59A40000 0x10000>,
+ <0x59A50000 0x10000>,
+ <0x59A80000 0x10000>, /* sai6 rx */
+ <0x59A90000 0x10000>, /* sai6 tx */
+ <0x59AA0000 0x10000>; /* sai7 tx */
+ dma-channels = <9>;
+ interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc1 */
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai6 */
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai7 */
+ interrupt-names = "edma3-chan0-rx", "edma3-chan1-rx", /* asrc1 */
+ "edma3-chan2-rx", "edma3-chan3-tx",
+ "edma3-chan4-tx", "edma3-chan5-tx",
+ "edma3-chan8-rx", "edma3-chan9-tx", /* sai6 */
+ "edma3-chan10-tx"; /* sai7 */
+ power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
+ <&pd IMX_SC_R_DMA_3_CH1>,
+ <&pd IMX_SC_R_DMA_3_CH2>,
+ <&pd IMX_SC_R_DMA_3_CH3>,
+ <&pd IMX_SC_R_DMA_3_CH4>,
+ <&pd IMX_SC_R_DMA_3_CH5>,
+ <&pd IMX_SC_R_DMA_3_CH8>,
+ <&pd IMX_SC_R_DMA_3_CH9>,
+ <&pd IMX_SC_R_DMA_3_CH10>;
+ power-domain-names = "edma3-chan0", "edma3-chan1",
+ "edma3-chan2", "edma3-chan3",
+ "edma3-chan4", "edma3-chan5",
+ "edma3-chan8", "edma3-chan9",
+ "edma3-chan10";
+};
+
+&asrc0 {
+ clocks = <&asrc0_lpcg 0>,
+ <&asrc0_lpcg 1>,
+ <&aud_pll_div0_lpcg 0>,
+ <&aud_pll_div1_lpcg 0>,
+ <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+ <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ power-domains = <&pd IMX_SC_R_ASRC_0>;
+};
+
+&esai0 {
+ power-domains = <&pd IMX_SC_R_ESAI_0>;
+};
+
+&spdif0 {
+ power-domains = <&pd IMX_SC_R_SPDIF_0>;
+};
+
+&spdif1 {
+ power-domains = <&pd IMX_SC_R_SPDIF_1>;
+};
+
+&sai0 {
+ power-domains = <&pd IMX_SC_R_SAI_0>;
+};
+
+&sai1 {
+ power-domains = <&pd IMX_SC_R_SAI_1>;
+};
+
+&sai2 {
+ power-domains = <&pd IMX_SC_R_SAI_2>;
+};
+
+&sai3 {
+ power-domains = <&pd IMX_SC_R_SAI_3>;
+};
+
+&asrc1 {
+ clocks = <&asrc1_lpcg 0>,
+ <&asrc1_lpcg 1>,
+ <&aud_pll_div0_lpcg 0>,
+ <&aud_pll_div1_lpcg 0>,
+ <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+ <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ power-domains = <&pd IMX_SC_R_ASRC_1>;
+};
+
+&amix {
+ dais = <&sai6>, <&sai7>;
+};
+
+&asrc0_lpcg {
+ clocks = <&audio_ipg_clk>,
+ <&audio_ipg_clk>;
+ bit-offset = <0 8>;
+ clock-output-names = "asrc0_lpcg_ipg_clk",
+ "asrc0_lpcg_mem_clk";
+};
+
+&esai0_lpcg {
+ bit-offset = <16 0>;
+ clock-output-names = "esai0_lpcg_extal_clk",
+ "esai0_lpcg_ipg_clk";
+};
+
+&spdif0_lpcg {
+ bit-offset = <20 16>;
+ clock-output-names = "spdif0_lpcg_tx_clk",
+ "spdif0_lpcg_gclkw";
+};
+
+&spdif1_lpcg {
+ bit-offset = <20 16>;
+ clock-output-names = "spdif1_lpcg_tx_clk",
+ "spdif1_lpcg_gclkw";
+};
+
+&sai0_lpcg {
+ bit-offset = <16 0>;
+ clock-output-names = "sai0_lpcg_mclk",
+ "sai0_lpcg_ipg_clk";
+};
+
+&sai1_lpcg {
+ bit-offset = <16 0>;
+ clock-output-names = "sai1_lpcg_mclk",
+ "sai1_lpcg_ipg_clk";
+};
+
+&sai2_lpcg {
+ bit-offset = <16 0>;
+ clock-output-names = "sai2_lpcg_mclk",
+ "sai2_lpcg_ipg_clk";
+};
+
+&sai3_lpcg {
+ bit-offset = <16 0>;
+ clock-output-names = "sai3_lpcg_mclk",
+ "sai3_lpcg_ipg_clk";
+};
+
+&asrc1_lpcg {
+ clocks = <&audio_ipg_clk>,
+ <&audio_ipg_clk>;
+ bit-offset = <0 8>;
+ clock-output-names = "asrc1_lpcg_ipg_clk",
+ "asrc1_lpcg_mem_clk";
+};
+
+&mqs0_lpcg {
+ bit-offset = <16 0>;
+ clock-output-names = "mqs0_lpcg_mclk",
+ "mqs0_lpcg_ipg_clk";
+};
+
+&dsp_lpcg {
+ status = "disabled";
+};
+
+&dsp_ram_lpcg {
+ status = "disabled";
+};
+
+&audio_subsys {
+ acm: acm@59e00000 {
+ compatible = "nxp,imx8qm-acm";
+ reg = <0x59e00000 0x1D0000>;
+ #clock-cells = <1>;
+ power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
+ <&pd IMX_SC_R_AUDIO_CLK_1>,
+ <&pd IMX_SC_R_MCLK_OUT_0>,
+ <&pd IMX_SC_R_MCLK_OUT_1>,
+ <&pd IMX_SC_R_AUDIO_PLL_0>,
+ <&pd IMX_SC_R_AUDIO_PLL_1>,
+ <&pd IMX_SC_R_ASRC_0>,
+ <&pd IMX_SC_R_ASRC_1>,
+ <&pd IMX_SC_R_ESAI_0>,
+ <&pd IMX_SC_R_ESAI_1>,
+ <&pd IMX_SC_R_SAI_0>,
+ <&pd IMX_SC_R_SAI_1>,
+ <&pd IMX_SC_R_SAI_2>,
+ <&pd IMX_SC_R_SAI_3>,
+ <&pd IMX_SC_R_SAI_4>,
+ <&pd IMX_SC_R_SAI_5>,
+ <&pd IMX_SC_R_SAI_6>,
+ <&pd IMX_SC_R_SAI_7>,
+ <&pd IMX_SC_R_SPDIF_0>,
+ <&pd IMX_SC_R_SPDIF_1>,
+ <&pd IMX_SC_R_MQS_0>;
+ };
+
+ sai4: sai@59080000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59080000 0x10000>;
+ interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai4_lpcg 1>,
+ <&clk_dummy>,
+ <&sai4_lpcg 0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx";
+ dmas = <&edma0 18 0 1>;
+ fsl,dataline = <0 0xf 0x0>;
+ power-domains = <&pd IMX_SC_R_SAI_4>;
+ status = "disabled";
+ };
+
+ sai5: sai@59090000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59090000 0x10000>;
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai5_lpcg 1>,
+ <&clk_dummy>,
+ <&sai5_lpcg 0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx";
+ dmas = <&edma0 19 0 0>;
+ fsl,dataline = <0 0x0 0xf>;
+ power-domains = <&pd IMX_SC_R_SAI_5>;
+ status = "disabled";
+ };
+
+ esai1: esai@59810000 {
+ compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai";
+ reg = <0x59810000 0x10000>;
+ interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&esai1_lpcg 1>,
+ <&esai1_lpcg 0>,
+ <&esai1_lpcg 1>,
+ <&clk_dummy>;
+ clock-names = "core", "extal", "fsys", "spba";
+ dmas = <&edma1 6 0 1>, <&edma1 7 0 0>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd IMX_SC_R_ESAI_1>;
+ status = "disabled";
+ };
+
+ sai6: sai@59820000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59820000 0x10000>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai6_lpcg 1>,
+ <&clk_dummy>,
+ <&sai6_lpcg 0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&edma1 8 0 1>, <&edma1 9 0 0>;
+ power-domains = <&pd IMX_SC_R_SAI_6>;
+ status = "disabled";
+ };
+
+ sai7: sai@59830000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59830000 0x10000>;
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai7_lpcg 1>,
+ <&clk_dummy>,
+ <&sai7_lpcg 0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx";
+ dmas = <&edma1 10 0 0>;
+ power-domains = <&pd IMX_SC_R_SAI_7>;
+ status = "disabled";
+ };
+
+ sai4_lpcg: clock-controller@59480000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59480000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <16 0>;
+ clock-output-names = "sai4_lpcg_mclk",
+ "sai4_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_4>;
+ status = "disabled";
+ };
+
+ sai5_lpcg: clock-controller@59490000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59490000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <16 0>;
+ clock-output-names = "sai5_lpcg_mclk",
+ "sai5_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_5>;
+ status = "disabled";
+ };
+
+ esai1_lpcg: clock-controller@59c10000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c10000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_ESAI1_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <16 0>;
+ clock-output-names = "esai1_lpcg_extal_clk",
+ "esai1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ESAI_1>;
+ };
+
+ sai6_lpcg: clock-controller@59c20000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <16 0>;
+ clock-output-names = "sai6_lpcg_mclk",
+ "sai6_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_6>;
+ };
+
+ sai7_lpcg: clock-controller@59c30000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c30000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ bit-offset = <16 0>;
+ clock-output-names = "sai7_lpcg_mclk",
+ "sai7_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_7>;
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/seco/include/imx8qm-ss-conn.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..d50856d38577b6362a8868a25716c8554d52d590
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qm-ss-conn.dtsi
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&conn_subsys {
+ usbh1: usb@5b0e0000 {
+ compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb",
+ "fsl,imx27-usb";
+ reg = <0x5b0e0000 0x200>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ phy_type = "hsic";
+ dr_mode = "host";
+ fsl,usbphy = <&usbphynop2>;
+ fsl,usbmisc = <&usbmisc2 0>;
+ clocks = <&usb2_lpcg 0>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ #stream-id-cells = <1>;
+ power-domains = <&pd IMX_SC_R_USB_1>;
+ status = "disabled";
+ };
+
+ usbmisc2: usbmisc@5b0e0200 {
+ #index-cells = <1>;
+ compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
+ reg = <0x5b0e0200 0x200>;
+ };
+
+ usbphynop2: usbphynop2 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&usb2_lpcg 1>;
+ clock-names = "main_clk";
+ power-domains = <&pd IMX_SC_R_USB_0_PHY>;
+ status = "disabled";
+ };
+};
+
+&fec1 {
+ compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
+ iommus = <&smmu 0x12 0x7f80>;
+};
+
+&fec2 {
+ compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
+ iommus = <&smmu 0x12 0x7f80>;
+};
+
+&usdhc1 {
+ compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc";
+ iommus = <&smmu 0x11 0x7f80>;
+};
+
+&usdhc2 {
+ compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc";
+ iommus = <&smmu 0x11 0x7f80>;
+};
+
+&usdhc3 {
+ compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc";
+ iommus = <&smmu 0x11 0x7f80>;
+};
+
+&usbotg3 {
+ iommus = <&smmu 0x4 0x7f80>;
+};
+
+&usbotg3_cdns3 {
+ iommus = <&smmu 0x4 0x7f80>;
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qm-ss-dc.dtsi b/arch/arm64/boot/dts/seco/include/imx8qm-ss-dc.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..e0c93f2aeddc033a2406171ca2a0b5c27db04098
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qm-ss-dc.dtsi
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2019 NXP
+ */
+
+&dpu1 {
+ compatible = "fsl,imx8qm-dpu";
+
+ dpu1_disp0: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ dpu1_disp0_hdmi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hdmi_disp>;
+ };
+
+ dpu1_disp0_mipi0: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi0_dsi_in>;
+ };
+ };
+
+ dpu1_disp1: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ dpu1_disp1_ldb1_ch0: endpoint@0 {
+ remote-endpoint = <&ldb1_ch0>;
+ };
+
+ dpu1_disp1_ldb1_ch1: endpoint@1 {
+ remote-endpoint = <&ldb1_ch1>;
+ };
+ };
+};
+
+&dpu2 {
+ compatible = "fsl,imx8qm-dpu";
+
+ dpu2_disp0: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ dpu2_disp0_mipi1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi1_dsi_in>;
+ };
+
+ };
+
+ dpu2_disp1: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ dpu2_disp1_ldb2_ch0: endpoint@0 {
+ remote-endpoint = <&ldb2_ch0>;
+ };
+
+ dpu2_disp1_ldb2_ch1: endpoint@1 {
+ remote-endpoint = <&ldb2_ch1>;
+ };
+ };
+};
+
+/ {
+ display-subsystem {
+ compatible = "fsl,imx-display-subsystem";
+ ports = <&dpu1_disp0>, <&dpu1_disp1>,
+ <&dpu2_disp0>, <&dpu2_disp1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qm-ss-ddr.dtsi b/arch/arm64/boot/dts/seco/include/imx8qm-ss-ddr.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..e47b12a765560fa765d50d9379d8623d04521dc6
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qm-ss-ddr.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&ddr_subsys {
+ ddr_pmu1: ddr-pmu@5c120000 {
+ compatible = "fsl,imx8-ddr-pmu";
+ reg = <0x5c120000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&ddr_pmu0 {
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/seco/include/imx8qm-ss-dma.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..2925d619512dd217eb105ebd2cb97ba0fe6fd61b
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qm-ss-dma.dtsi
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&dma_subsys {
+ lpuart4: serial@5a0a0000 {
+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+ reg = <0x5a0a0000 0x1000>;
+ interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&uart4_lpcg 1>, <&uart4_lpcg 0>;
+ clock-names = "ipg", "baud";
+ assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&pd IMX_SC_R_UART_4>;
+ power-domain-names = "uart";
+ dma-names = "tx","rx";
+ dmas = <&edma2 21 0 0>,
+ <&edma2 20 0 1>;
+ status = "disabled";
+ };
+
+ uart4_lpcg: clock-controller@5a4a0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a4a0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "uart4_lpcg_baud_clk",
+ "uart4_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_4>;
+ };
+
+ i2c4: i2c@5a840000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x5a840000 0x4000>;
+ interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&i2c4_lpcg 0>,
+ <&i2c4_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_4>;
+ status = "disabled";
+ };
+
+ i2c4_lpcg: clock-controller@5ac40000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac40000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "i2c4_lpcg_clk",
+ "i2c4_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_4>;
+ };
+
+ can1_lpcg: clock-controller@5ace0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ace0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>, <&dma_ipg_clk>;
+ bit-offset = <0 16 20>;
+ clock-output-names = "can1_lpcg_pe_clk",
+ "can1_lpcg_ipg_clk",
+ "can1_lpcg_chi_clk";
+ power-domains = <&pd IMX_SC_R_CAN_1>;
+ };
+
+ can2_lpcg: clock-controller@5acf0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5acf0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>, <&dma_ipg_clk>;
+ bit-offset = <0 16 20>;
+ clock-output-names = "can2_lpcg_pe_clk",
+ "can2_lpcg_ipg_clk",
+ "can2_lpcg_chi_clk";
+ power-domains = <&pd IMX_SC_R_CAN_2>;
+ };
+};
+
+&flexcan1 {
+ fsl,clk-source = <1>;
+};
+
+&flexcan2 {
+ clocks = <&can1_lpcg 1>,
+ <&can1_lpcg 0>;
+ assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>;
+ fsl,clk-source = <1>;
+};
+
+&flexcan3 {
+ clocks = <&can2_lpcg 1>,
+ <&can2_lpcg 0>;
+ assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>;
+ fsl,clk-source = <1>;
+};
+
+&lpspi2 {
+ compatible = "fsl,imx8qm-lpspi", "fsl,imx7ulp-spi";
+};
+
+/* edma0 called in imx8qm RM with the same address in edma2 of imx8qxp */
+&edma2 {
+ reg = <0x5a1f0000 0x10000>,
+ <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */
+ <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */
+ <0x5a220000 0x10000>, /* channel2 LPSPI1 rx */
+ <0x5a230000 0x10000>, /* channel3 LPSPI1 tx */
+ <0x5a240000 0x10000>, /* channel4 LPSPI2 rx */
+ <0x5a250000 0x10000>, /* channel5 LPSPI2 tx */
+ <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */
+ <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */
+ <0x5a2c0000 0x10000>, /* channel12 UART0 rx */
+ <0x5a2d0000 0x10000>, /* channel13 UART0 tx */
+ <0x5a2e0000 0x10000>, /* channel14 UART1 rx */
+ <0x5a2f0000 0x10000>, /* channel15 UART1 tx */
+ <0x5a300000 0x10000>, /* channel16 UART2 rx */
+ <0x5a310000 0x10000>, /* channel17 UART2 tx */
+ <0x5a320000 0x10000>, /* channel18 UART3 rx */
+ <0x5a330000 0x10000>, /* channel19 UART3 tx */
+ <0x5a340000 0x10000>, /* channel20 UART4 rx */
+ <0x5a350000 0x10000>; /* channel21 UART4 tx */
+ #dma-cells = <3>;
+ dma-channels = <18>;
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx",
+ "edma0-chan2-rx", "edma0-chan3-tx",
+ "edma0-chan4-rx", "edma0-chan5-tx",
+ "edma0-chan6-rx", "edma0-chan7-tx",
+ "edma0-chan12-rx", "edma0-chan13-tx",
+ "edma0-chan14-rx", "edma0-chan15-tx",
+ "edma0-chan16-rx", "edma0-chan17-tx",
+ "edma0-chan18-rx", "edma0-chan19-tx",
+ "edma0-chan20-rx", "edma0-chan21-tx";
+ power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
+ <&pd IMX_SC_R_DMA_0_CH1>,
+ <&pd IMX_SC_R_DMA_0_CH2>,
+ <&pd IMX_SC_R_DMA_0_CH3>,
+ <&pd IMX_SC_R_DMA_0_CH4>,
+ <&pd IMX_SC_R_DMA_0_CH5>,
+ <&pd IMX_SC_R_DMA_0_CH6>,
+ <&pd IMX_SC_R_DMA_0_CH7>,
+ <&pd IMX_SC_R_DMA_0_CH12>,
+ <&pd IMX_SC_R_DMA_0_CH13>,
+ <&pd IMX_SC_R_DMA_0_CH14>,
+ <&pd IMX_SC_R_DMA_0_CH15>,
+ <&pd IMX_SC_R_DMA_0_CH16>,
+ <&pd IMX_SC_R_DMA_0_CH17>,
+ <&pd IMX_SC_R_DMA_0_CH18>,
+ <&pd IMX_SC_R_DMA_0_CH19>,
+ <&pd IMX_SC_R_DMA_0_CH20>,
+ <&pd IMX_SC_R_DMA_0_CH21>;
+ power-domain-names = "edma0-chan0", "edma0-chan1",
+ "edma0-chan2", "edma0-chan3",
+ "edma0-chan4", "edma0-chan5",
+ "edma0-chan6", "edma0-chan7",
+ "edma0-chan12", "edma0-chan13",
+ "edma0-chan14", "edma0-chan15",
+ "edma0-chan16", "edma0-chan17",
+ "edma0-chan18", "edma0-chan19",
+ "edma0-chan20", "edma0-chan21";
+ status = "okay";
+};
+
+&lpuart0 {
+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+};
+
+&lpuart1 {
+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+ dmas = <&edma2 15 0 0>,
+ <&edma2 14 0 1>;
+};
+
+&lpuart2 {
+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+ dmas = <&edma2 17 0 0>,
+ <&edma2 16 0 1>;
+};
+
+&lpuart3 {
+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+ dmas = <&edma2 19 0 0>,
+ <&edma2 18 0 1>;
+};
+
+&i2c0 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&i2c1 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&i2c2 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&i2c3 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qm-ss-gpu.dtsi b/arch/arm64/boot/dts/seco/include/imx8qm-ss-gpu.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..90b670b15276a817a90e8685804553c02c720ff6
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qm-ss-gpu.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&gpu_3d0 {
+ assigned-clock-rates = <800000000>, <1000000000>;
+ fsl,sc_gpu_pid = <IMX_SC_R_GPU_0_PID0>;
+};
+
+&gpu1_subsys {
+ imx8_gpu_ss: imx8_gpu1_ss {
+ compatible = "fsl,imx8qm-gpu", "fsl,imx8-gpu-ss";
+ cores = <&gpu_3d0>, <&gpu_3d1>;
+ reg = <0x80000000 0x80000000>, <0x0 0x10000000>;
+ reg-names = "phys_baseaddr", "contiguous_mem";
+ depth-compression = <0>;
+ /*<freq-kHz vol-uV>*/
+ operating-points = <
+ /*overdrive*/ 800000 0 /*The first tuple is for core clock frequency*/
+ 1000000 0 /*The second tuple is for shader clock frequency*/
+ /*nominal*/ 650000 0
+ 700000 0
+ /*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/
+ >;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qm-ss-hdmi-rx.dtsi b/arch/arm64/boot/dts/seco/include/imx8qm-ss-hdmi-rx.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..02db56800ad11f46102b9a4ed4ff676b9e34dc2e
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qm-ss-hdmi-rx.dtsi
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ * Sandor Yu <Sandor.yu@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+&img_subsys {
+ irqsteer_hdmi_rx: irqsteer@58260000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x58260000 0x1000>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ clocks = <&hdmi_rx_ipg>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_HDMI_RX>;
+ status = "disabled";
+ };
+
+ hdmi_rx_ipg: clock-hdmi-rx-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "hdmi_rx_ipg_clk";
+ };
+
+ hdmi_rx_dig_pll: clock-hdmi-rx-dig-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "hdmi_rx_dig_pll_clk";
+ };
+
+ hdmi_rx_lpcg_gpio_ipg_s: clock-controller@58263000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58263000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&hdmi_rx_ipg>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_rx_lpcg_gpio_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX>;
+ status = "disabled";
+ };
+
+ hdmi_rx_lpcg_pwm_ipg: clock-controller@58263004 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58263004 0x4>;
+ #clock-cells = <1>;
+ clocks = <&hdmi_lpcg_pwm_ipg_s 0>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_rx_lpcg_pwm_ipg_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX_PWM_0>;
+ status = "disabled";
+ };
+
+ hdmi_lpcg_pwm_ipg_s: clock-controller@58263008 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58263008 0x4>;
+ #clock-cells = <1>;
+ clocks = <&hdmi_rx_ipg>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_lpcg_pwm_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX_PWM_0>;
+ status = "disabled";
+ };
+
+ hdmi_rx_lpcg_pwm: clock-controller@5826300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5826300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_HDMI_RX_PWM_0 IMX_SC_PM_CLK_MISC2>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_rx_lpcg_pwm_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX_PWM_0>;
+ status = "disabled";
+ };
+
+ hdmi_rx_lpcg_i2c0: clock-controller@58263010 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58263010 0x4>;
+ #clock-cells = <1>;
+ clocks = <&hdmi_rx_lpcg_i2c0_div 0>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_rx_lpcg_i2c0_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>;
+ status = "disabled";
+ };
+
+ hdmi_rx_lpcg_i2c0_div: clock-controller@58263014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58263014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_HDMI_RX_I2C_0 IMX_SC_PM_CLK_MISC2>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_rx_lpcg_i2c0_div_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>;
+ status = "disabled";
+ };
+
+ hdmi_rx_lpcg_i2c0_ipg: clock-controller@58263018 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58263018 0x4>;
+ #clock-cells = <1>;
+ clocks = <&hdmi_rx_lpcg_i2c0_ipg_s 0>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_rx_lpcg_i2c0_ipg_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>;
+ status = "disabled";
+ };
+
+ hdmi_rx_lpcg_i2c0_ipg_s: clock-controller@5826301c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5826301c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&hdmi_rx_ipg>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_rx_lpcg_i2c0_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>;
+ status = "disabled";
+ };
+
+ hdmi_rx_lpcg_sink_p: clock-controller@58263020 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58263020 0x4>;
+ #clock-cells = <1>;
+ clocks = <&hdmi_rx_ipg>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_rx_lpcg_sink_p_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX>;
+ status = "disabled";
+ };
+
+ hdmi_rx_lpcg_sink_s: clock-controller@58263024 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58263024 0x4>;
+ #clock-cells = <1>;
+ clocks = <&hdmi_rx_ipg>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_rx_lpcg_sink_s_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX>;
+ status = "disabled";
+ };
+
+ hdmi_rx_lpcg_hd_core: clock-controller@58263028 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58263028 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC2>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_rx_lpcg_hd_core_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX>;
+ status = "disabled";
+ };
+
+ hdmi_rx_lpcg_pxl: clock-controller@5826302c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5826302c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC3>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_rx_lpcg_pxl_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX>;
+ status = "disabled";
+ };
+
+ hdmi_rx_lpcg_enc: clock-controller@58263030 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x58263030 0x4>;
+ #clock-cells = <1>;
+ clocks = <&hdmi_rx_lpcg_pxl 0>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_rx_lpcg_enc_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX>;
+ status = "disabled";
+ };
+
+ i2c0_hdmi_rx: i2c@58266000 {
+ compatible = "fsl,imx8qm-lpi2c";
+ reg = <0x58266000 0x1000>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&irqsteer_hdmi_rx>;
+ clocks = <&hdmi_rx_lpcg_i2c0>,
+ <&hdmi_rx_lpcg_i2c0_ipg>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_HDMI_RX_I2C_0 IMX_SC_PM_CLK_MISC2>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>;
+ status = "disabled";
+ };
+};
+
+&cameradev {
+ hdmi_rx: hdmi_rx@58268000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "cdn,imx8qm-hdmirx";
+ reg = <0x58268000 0x10000>, /* HDP Controller */
+ <0x58261000 0x1000>; /* HDP SubSystem CSR */
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
+ <13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "plug_in", "plug_out";
+ interrupt-parent = <&irqsteer_hdmi_rx>;
+ clocks = <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC1>,
+ <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC3>,
+ <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC4>,
+ <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC0>,
+ <&hdmi_rx_lpcg_sink_p 0>,
+ <&hdmi_rx_lpcg_sink_s 0>,
+ <&hdmi_rx_lpcg_enc 0>,
+ <&hdmi_rx_pxl_link_lpcg 0>;
+ clock-names = "ref_clk",
+ "pxl_clk", "i2s_clk", "spdif_clk",
+ "lpcg_pclk", "lpcg_sclk", "lpcg_enc_clk",
+ "lpcg_pxl_link_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_RX>;
+ power-domain-names = "hdmi_rx";
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qm-ss-hdmi.dtsi b/arch/arm64/boot/dts/seco/include/imx8qm-ss-hdmi.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..3f0ca0616737d7fa95784361da34b1c12d9ccda9
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qm-ss-hdmi.dtsi
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Sandor Yu <Sandor.yu@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+/ {
+ hdmi_subsys: bus@56260000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x56260000 0x0 0x56260000 0x10000>;
+
+ irqsteer_hdmi: irqsteer@56260000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x56260000 0x1000>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ clocks = <&hdmi_lpcg_lis_ipg 0>;
+ clock-names = "ipg";
+ assigned-clocks = <&clk IMX_SC_R_HDMI_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>;
+ assigned-clock-rates = <800000000>, <84375000>;
+ power-domains = <&pd IMX_SC_R_HDMI>;
+ status = "disabled";
+ };
+
+ hdmi_lpcg_i2c0: clock-controller@56263000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56263000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_HDMI_I2C_0 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>;
+ bit-offset = <0 16>;
+ clock-output-names = "hdmi_lpcg_i2c0_clk",
+ "hdmi_lpcg_i2c0_ipg_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_I2C_0>;
+ status = "disabled";
+ };
+
+ hdmi_lpcg_lis_ipg: clock-controller@56263004 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56263004 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>;
+ bit-offset = <16>;
+ clock-output-names = "hdmi_lpcg_lis_ipg_clk";
+ power-domains = <&pd IMX_SC_R_HDMI>;
+ status = "disabled";
+ };
+
+ hdmi_lpcg_pwm_ipg: clock-controller@56263008 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56263008 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>;
+ bit-offset = <16>;
+ clock-output-names = "hdmi_lpcg_pwm_ipg_clk";
+ power-domains = <&pd IMX_SC_R_HDMI>;
+ status = "disabled";
+ };
+
+ hdmi_lpcg_i2s: clock-controller@5626300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5626300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_HDMI_I2S IMX_SC_PM_CLK_MISC0>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_lpcg_i2s_clk";
+ power-domains = <&pd IMX_SC_R_HDMI_I2S>;
+ status = "disabled";
+ };
+
+ hdmi_lpcg_gpio_ipg: clock-controller@56263010 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56263010 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>;
+ bit-offset = <16>;
+ clock-output-names = "hdmi_lpcg_gpio_ipg_clk";
+ power-domains = <&pd IMX_SC_R_HDMI>;
+ status = "disabled";
+ };
+
+ hdmi_lpcg_msi_hclk: clock-controller@56263014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56263014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_lpcg_msi_hclk_clk";
+ power-domains = <&pd IMX_SC_R_HDMI>;
+ status = "disabled";
+ };
+
+ hdmi_lpcg_pxl: clock-controller@56263018 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56263018 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>;
+ bit-offset = <0>;
+ clock-output-names = "hdmi_lpcg_pxl_clk";
+ power-domains = <&pd IMX_SC_R_HDMI>;
+ status = "disabled";
+ };
+
+ hdmi_lpcg_phy: clock-controller@5626301c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5626301c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>,
+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>;
+ bit-offset = <0 16>;
+ clock-output-names = "hdmi_lpcg_phy_vif_clk",
+ "hdmi_lpcg_phy_pclk";
+ power-domains = <&pd IMX_SC_R_HDMI>;
+ status = "disabled";
+ };
+
+ hdmi_lpcg_apb_mux_csr: clock-controller@56263020 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56263020 0x4>;
+ #clock-cells = <1>;
+ clocks = <&hdmi_lpcg_apb 0>;
+ bit-offset = <16>;
+ clock-output-names = "hdmi_lpcg_apb_mux_csr_clk";
+ power-domains = <&pd IMX_SC_R_HDMI>;
+ status = "disabled";
+ };
+
+ hdmi_lpcg_apb_mux_ctrl: clock-controller@56263024 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56263024 0x4>;
+ #clock-cells = <1>;
+ clocks = <&hdmi_lpcg_apb 0>;
+ bit-offset = <16>;
+ clock-output-names = "hdmi_lpcg_apb_mux_ctrl_clk";
+ power-domains = <&pd IMX_SC_R_HDMI>;
+ status = "disabled";
+ };
+
+ hdmi_lpcg_apb: clock-controller@56263028 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56263028 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>;
+ bit-offset = <16>;
+ clock-output-names = "hdmi_lpcg_apb_clk";
+ power-domains = <&pd IMX_SC_R_HDMI>;
+ status = "disabled";
+ };
+
+ i2c0_hdmi: i2c@56266000 {
+ compatible = "fsl,imx8qm-lpi2c";
+ reg = <0x56266000 0x1000>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&irqsteer_hdmi>;
+ clocks = <&hdmi_lpcg_i2c0 0>,
+ <&hdmi_lpcg_i2c0 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_HDMI_I2C_0 IMX_SC_PM_CLK_MISC2>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_HDMI_I2C_0>;
+ status = "disabled";
+ };
+
+ hdmi:hdmi@56268000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x56268000 0x1000>,
+ <0x56261000 0x1000>;
+ interrupt-parent = <&irqsteer_hdmi>;
+ interrupts = <10>, <13>;
+ interrupt-names = "plug_in", "plug_out";
+ firmware-name = "hdmitxfw.bin";
+ status = "disabled";
+
+ clocks = <&clk IMX_SC_R_HDMI_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>,
+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC3>,
+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>,
+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC1>,
+ <&hdmi_lpcg_phy 1>,
+ <&hdmi_lpcg_msi_hclk 0>,
+ <&hdmi_lpcg_pxl 0>,
+ <&hdmi_lpcg_phy 0>,
+ <&hdmi_lpcg_lis_ipg 0>,
+ <&hdmi_lpcg_apb 0>,
+ <&hdmi_lpcg_apb_mux_csr 0>,
+ <&hdmi_lpcg_apb_mux_ctrl 0>,
+ <&clk IMX_SC_R_HDMI_I2S IMX_SC_PM_CLK_BYPASS>,
+ <&hdmi_lpcg_i2s 0>;
+ clock-names = "dig_pll", "av_pll", "clk_ipg",
+ "clk_core", "clk_pxl", "clk_pxl_mux",
+ "clk_pxl_link", "lpcg_hdp", "lpcg_msi",
+ "lpcg_pxl", "lpcg_vif", "lpcg_lis",
+ "lpcg_apb", "lpcg_apb_csr", "lpcg_apb_ctrl",
+ "clk_i2s_bypass", "lpcg_i2s";
+ assigned-clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC3>,
+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>,
+ <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC1>;
+ assigned-clock-parents = <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>;
+ power-domains = <&pd IMX_SC_R_HDMI>,
+ <&pd IMX_SC_R_HDMI_PLL_0>,
+ <&pd IMX_SC_R_HDMI_PLL_1>;
+ power-domain-names = "hdmi", "pll0", "pll1";
+
+ port@0 {
+ reg = <0>;
+ hdmi_disp: endpoint {
+ remote-endpoint = <&dpu1_disp0_hdmi>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/seco/include/imx8qm-ss-hsio.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..09fde1445c456aa6fc0323c317d4ad3bf610959b
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qm-ss-hsio.dtsi
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Richard Zhu <hongxing.zhu@nxp.com>
+ */
+
+&hsio_subsys {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pciea_lpcg: clock-controller@5f050000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f050000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>;
+ bit-offset = <16 20 24>;
+ clock-output-names = "hsio_pciea_mstr_axi_clk",
+ "hsio_pciea_slv_axi_clk",
+ "hsio_pciea_dbi_axi_clk";
+ power-domains = <&pd IMX_SC_R_PCIE_A>;
+ };
+
+ sata_lpcg: clock-controller@5f070000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f070000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_axi_clk>;
+ bit-offset = <16>;
+ clock-output-names = "hsio_sata_clk";
+ power-domains = <&pd IMX_SC_R_SATA_0>;
+ };
+
+ phyx2_lpcg: clock-controller@5f080000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f080000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_refa_clk>, <&hsio_per_clk>,
+ <&hsio_refa_clk>, <&hsio_per_clk>;
+ bit-offset = <0 4 16 20>;
+ clock-output-names = "hsio_phyx2_pclk_0",
+ "hsio_phyx2_pclk_1",
+ "hsio_phyx2_apbclk_0",
+ "hsio_phyx2_apbclk_1";
+ power-domains = <&pd IMX_SC_R_SERDES_0>;
+ };
+
+ phyx1_lpcg: clock-controller@5f090000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f090000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_refa_clk>, <&hsio_per_clk>,
+ <&hsio_per_clk>, <&hsio_per_clk>;
+ bit-offset = <0 4 8 16>;
+ clock-output-names = "hsio_phyx1_pclk",
+ "hsio_phyx1_epcs_tx_clk",
+ "hsio_phyx1_epcs_rx_clk",
+ "hsio_phyx1_apb_clk";
+ power-domains = <&pd IMX_SC_R_SERDES_1>;
+ };
+
+ phyx2_crr0_lpcg: clock-controller@5f0a0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f0a0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_per_clk>;
+ bit-offset = <16>;
+ clock-output-names = "hsio_phyx2_per_clk";
+ power-domains = <&pd IMX_SC_R_SERDES_0>;
+ };
+
+ pciea_crr2_lpcg: clock-controller@5f0c0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f0c0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_per_clk>;
+ bit-offset = <16>;
+ clock-output-names = "hsio_pciea_per_clk";
+ power-domains = <&pd IMX_SC_R_PCIE_A>;
+ };
+
+ sata_crr4_lpcg: clock-controller@5f0e0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f0e0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_per_clk>;
+ bit-offset = <16>;
+ clock-output-names = "hsio_sata_per_clk";
+ power-domains = <&pd IMX_SC_R_SATA_0>;
+ };
+
+ pciea: pcie@0x5f000000 {
+ compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
+ reg = <0x5f000000 0x10000>, /* Controller reg */
+ <0x6ff00000 0x80000>, /* PCI cfg space */
+ <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */
+ reg-names = "dbi", "config", "hsio";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x00000000 0x6ff80000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x60000000 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ num-viewport = <4>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+ interrupt-names = "msi", "dma";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic 0 73 4>,
+ <0 0 0 2 &gic 0 74 4>,
+ <0 0 0 3 &gic 0 75 4>,
+ <0 0 0 4 &gic 0 76 4>;
+ /*
+ * Set these clocks in default, then clocks should be
+ * refined for exact hw design of imx8 pcie.
+ */
+ clocks = <&pciea_lpcg 0>,
+ <&pciea_lpcg 1>,
+ <&pciea_lpcg 2>,
+ <&phyx2_lpcg 0>,
+ <&phyx2_crr0_lpcg 0>,
+ <&pciea_crr2_lpcg 0>,
+ <&misc_crr5_lpcg 0>;
+ clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
+ "pcie_phy", "phy_per", "pcie_per", "misc_per";
+ power-domains = <&pd IMX_SC_R_PCIE_A>,
+ <&pd IMX_SC_R_SERDES_0>,
+ <&pd IMX_SC_R_HSIO_GPIO>;
+ power-domain-names = "pcie", "pcie_phy", "hsio_gpio";
+ fsl,max-link-speed = <3>;
+ hsio-cfg = <PCIEAX1PCIEBX1SATA>;
+ local-addr = <0x40000000>;
+ status = "disabled";
+ };
+
+ pciea_ep: pcie_ep@0x5f000000 {
+ compatible = "fsl,imx8qm-pcie-ep";
+ reg = <0x5f000000 0x00010000>,
+ <0x5f080000 0xf0000>, /* lpcg, csr, msic, gpio */
+ <0x60000000 0x10000000>;
+ reg-names = "regs", "hsio", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+ interrupt-names = "dma";
+ /*
+ * Set these clocks in default, then clocks should be
+ * refined for exact hw design of imx8 pcie.
+ */
+ clocks = <&pciea_lpcg 0>,
+ <&pciea_lpcg 1>,
+ <&pciea_lpcg 2>,
+ <&phyx2_lpcg 0>,
+ <&phyx2_crr0_lpcg 0>,
+ <&pciea_crr2_lpcg 0>,
+ <&misc_crr5_lpcg 0>;
+ clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
+ "pcie_phy", "phy_per", "pcie_per", "misc_per";
+ power-domains = <&pd IMX_SC_R_PCIE_A>,
+ <&pd IMX_SC_R_SERDES_0>,
+ <&pd IMX_SC_R_HSIO_GPIO>;
+ power-domain-names = "pcie", "pcie_phy", "hsio_gpio";
+ fsl,max-link-speed = <3>;
+ hsio-cfg = <PCIEAX1PCIEBX1SATA>;
+ local-addr = <0x40000000>;
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
+ status = "disabled";
+ };
+
+ pcieb: pcie@0x5f010000 {
+ compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
+ reg = <0x5f010000 0x10000>, /* Controller reg */
+ <0x7ff00000 0x80000>, /* PCI cfg space */
+ <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */
+ reg-names = "dbi", "config", "hsio";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x00000000 0x7ff80000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x70000000 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ num-viewport = <4>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+ interrupt-names = "msi", "dma";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic 0 105 4>,
+ <0 0 0 2 &gic 0 106 4>,
+ <0 0 0 3 &gic 0 107 4>,
+ <0 0 0 4 &gic 0 108 4>;
+ clocks = <&pcieb_lpcg 0>,
+ <&pcieb_lpcg 1>,
+ <&pcieb_lpcg 2>,
+ <&phyx2_lpcg 1>,
+ <&phyx2_lpcg 0>,
+ <&phyx2_crr0_lpcg 0>,
+ <&pcieb_crr3_lpcg 0>,
+ <&pciea_crr2_lpcg 0>,
+ <&misc_crr5_lpcg 0>;
+ clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
+ "pcie_phy", "pcie_phy_pclk", "phy_per",
+ "pcie_per", "pciex2_per", "misc_per";
+ power-domains = <&pd IMX_SC_R_PCIE_B>,
+ <&pd IMX_SC_R_PCIE_A>,
+ <&pd IMX_SC_R_SERDES_0>,
+ <&pd IMX_SC_R_HSIO_GPIO>;
+ power-domain-names = "pcie", "pcie_per", "pcie_phy",
+ "hsio_gpio";
+ fsl,max-link-speed = <3>;
+ hsio-cfg = <PCIEAX1PCIEBX1SATA>;
+ local-addr = <0x80000000>;
+ status = "disabled";
+ };
+
+ sata: sata@5f020000 {
+ compatible = "fsl,imx8qm-ahci";
+ reg = <0x5f020000 0x10000>, /* Controller reg */
+ <0x5f1a0000 0x10000>, /* PHY reg */
+ <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */
+ reg-names = "ctl", "phy", "hsio";
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sata_lpcg 0>,
+ <&phyx1_lpcg 0>,
+ <&phyx1_lpcg 1>,
+ <&phyx1_lpcg 2>,
+ <&phyx2_crr0_lpcg 0>,
+ <&phyx1_crr1_lpcg 0>,
+ <&pciea_crr2_lpcg 0>,
+ <&pcieb_crr3_lpcg 0>,
+ <&sata_crr4_lpcg 0>,
+ <&misc_crr5_lpcg 0>,
+ <&phyx2_lpcg 0>,
+ <&phyx2_lpcg 1>,
+ <&phyx1_lpcg 3>;
+ clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx",
+ "per_clk0", "per_clk1", "per_clk2",
+ "per_clk3", "per_clk4", "per_clk5",
+ "phy_pclk0", "phy_pclk1", "phy_apbclk";
+ power-domains = <&pd IMX_SC_R_SATA_0>,
+ <&pd IMX_SC_R_PCIE_A>,
+ <&pd IMX_SC_R_PCIE_B>,
+ <&pd IMX_SC_R_SERDES_0>,
+ <&pd IMX_SC_R_SERDES_1>,
+ <&pd IMX_SC_R_HSIO_GPIO>;
+ fsl,sc_rsrc_id = <IMX_SC_R_SATA_0>;
+ iommus = <&smmu 0x13 0x7f80>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qm-ss-img.dtsi b/arch/arm64/boot/dts/seco/include/imx8qm-ss-img.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..a1baeeac02fe683e5a7ef732d5981a98c4acc05b
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qm-ss-img.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+&pi0_pxl_lpcg {
+ status = "disabled";
+};
+
+&pi0_ipg_lpcg {
+ status = "disabled";
+};
+
+&pi0_misc_lpcg {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/seco/include/imx8qm-ss-lsio.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..6b78433162453cfaf854213e04553f8018a7c769
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qm-ss-lsio.dtsi
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+&lsio_subsys {
+ lsio_mu6: mailbox@5d210000 {
+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+ reg = <0x5d210000 0x10000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_MU_6A>;
+ };
+
+ lsio_mu8: mailbox@5d230000 {
+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+ reg = <0x5d230000 0x10000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_MU_8A>;
+ status = "disabled";
+ };
+
+ lsio_mu8b: mailbox@5d2c0000 {
+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+ reg = <0x5d2c0000 0x10000>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ fsl,mu-side-b;
+ power-domains = <&pd IMX_SC_R_MU_8B>;
+ status = "disabled";
+ };
+
+};
+
+&lsio_gpio0 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio1 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio2 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio3 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio4 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio5 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio6 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio7 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_mu0 {
+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu1 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu2 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu3 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu4 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/seco/include/imx8qm-ss-lvds.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..8986f52e5b3ab21f89a5cf1694094b937bc133d6
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qm-ss-lvds.dtsi
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2019 NXP
+ */
+
+/ {
+ lvds_ipg_clk: clock-lvds-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "lvds_ipg_clk";
+ };
+
+ lvds1_subsys: bus@56240000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x56240000 0x0 0x56240000 0x10000>;
+
+ lvds0_ipg_clk: clock-lvds-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "lvds0_ipg_clk";
+ };
+
+ lvds0_lis_lpcg: clock-controller@56243000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&lvds0_ipg_clk>;
+ bit-offset = <16>;
+ clock-output-names = "lvds0_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+ };
+
+ lvds0_pwm_lpcg: clock-controller@5624300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5624300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&lvds0_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "lvds0_pwm_lpcg_clk",
+ "lvds0_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>;
+ };
+
+ lvds0_i2c0_lpcg: clock-controller@56243010 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243010 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&lvds0_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "lvds0_i2c0_lpcg_clk",
+ "lvds0_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
+ };
+
+ lvds0_i2c1_lpcg: clock-controller@56243014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&lvds0_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "lvds0_i2c1_lpcg_clk",
+ "lvds0_i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
+ };
+
+ irqsteer_lvds0: irqsteer@56240000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x56240000 0x1000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ clocks = <&lvds0_lis_lpcg 0>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+ };
+
+ lvds0_region: lvds_region@56241000 {
+ compatible = "syscon";
+ reg = <0x56241000 0xf0>;
+ };
+
+ ldb1_phy: ldb_phy@56241000 {
+ compatible = "mixel,lvds-phy";
+ reg = <0x56241000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
+ clock-names = "phy";
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+ status = "disabled";
+
+ ldb1_phy1: port@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ ldb1_phy2: port@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
+ ldb1: ldb@562410e0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qm-ldb";
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+ clock-names = "pixel", "bypass";
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+ gpr = <&lvds0_region>;
+ status = "disabled";
+
+ lvds-channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ phys = <&ldb1_phy1>;
+ phy-names = "ldb_phy";
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ ldb1_ch0: endpoint {
+ remote-endpoint = <&dpu1_disp1_ldb1_ch0>;
+ };
+ };
+ };
+
+ lvds-channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ phys = <&ldb1_phy2>;
+ phy-names = "ldb_phy";
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ ldb1_ch1: endpoint {
+ remote-endpoint = <&dpu1_disp1_ldb1_ch1>;
+ };
+ };
+ };
+ };
+
+ pwm_lvds0: pwm@56244000 {
+ compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+ reg = <0x56244000 0x1000>;
+ clocks = <&lvds0_pwm_lpcg 0>,
+ <&lvds0_pwm_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <2>;
+ power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>;
+ status = "disabled";
+ };
+
+ i2c0_lvds0: i2c@56246000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x56246000 0x1000>;
+ interrupts = <8>;
+ interrupt-parent = <&irqsteer_lvds0>;
+ clocks = <&lvds0_i2c0_lpcg 0>,
+ <&lvds0_i2c0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
+ status = "disabled";
+ };
+
+ i2c1_lvds0: i2c@56247000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x56247000 0x1000>;
+ interrupts = <9>;
+ interrupt-parent = <&irqsteer_lvds0>;
+ clocks = <&lvds0_i2c0_lpcg 0>,
+ <&lvds0_i2c0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
+ status = "disabled";
+ };
+ };
+
+ lvds2_subsys: bus@57240000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x57240000 0x0 0x57240000 0x10000>;
+
+ lvds1_ipg_clk: clock-lvds-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "lvds1_ipg_clk";
+ };
+
+ lvds1_lis_lpcg: clock-controller@57243000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57243000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&lvds1_ipg_clk>;
+ bit-offset = <16>;
+ clock-output-names = "lvds1_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1>;
+ };
+
+ lvds1_pwm_lpcg: clock-controller@5724300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5724300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&lvds1_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "lvds1_pwm_lpcg_clk",
+ "lvds1_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+ };
+
+ lvds1_i2c0_lpcg: clock-controller@57243010 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57243010 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&lvds1_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "lvds1_i2c0_lpcg_clk",
+ "lvds1_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+ };
+
+ lvds1_i2c1_lpcg: clock-controller@57243014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57243014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&lvds1_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "lvds1_i2c1_lpcg_clk",
+ "lvds1_i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+ };
+
+ irqsteer_lvds1: irqsteer@57240000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x57240000 0x1000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ clocks = <&lvds1_lis_lpcg 0>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_LVDS_1>;
+ };
+
+ lvds1_region: lvds_region@57241000 {
+ compatible = "syscon";
+ reg = <0x57241000 0xf0>;
+ };
+
+ ldb2_phy: ldb_phy@57241000 {
+ compatible = "mixel,lvds-phy";
+ reg = <0x57241000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_PHY>;
+ clock-names = "phy";
+ power-domains = <&pd IMX_SC_R_LVDS_1>;
+ status = "disabled";
+
+ ldb2_phy1: port@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ ldb2_phy2: port@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
+ ldb2: ldb@572410e0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qm-ldb";
+ clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>;
+ clock-names = "pixel", "bypass";
+ power-domains = <&pd IMX_SC_R_LVDS_1>;
+ gpr = <&lvds1_region>;
+ status = "disabled";
+
+ lvds-channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ phys = <&ldb2_phy1>;
+ phy-names = "ldb_phy";
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ ldb2_ch0: endpoint {
+ remote-endpoint = <&dpu2_disp1_ldb2_ch0>;
+ };
+ };
+ };
+
+ lvds-channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ phys = <&ldb2_phy2>;
+ phy-names = "ldb_phy";
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ ldb2_ch1: endpoint {
+ remote-endpoint = <&dpu2_disp1_ldb2_ch1>;
+ };
+ };
+ };
+ };
+
+ pwm_lvds1: pwm@57244000 {
+ compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+ reg = <0x57244000 0x1000>;
+ clocks = <&lvds1_pwm_lpcg 0>,
+ <&lvds1_pwm_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <2>;
+ power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+ status = "disabled";
+ };
+
+ i2c0_lvds1: i2c@57246000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x57246000 0x1000>;
+ interrupts = <8>;
+ interrupt-parent = <&irqsteer_lvds1>;
+ clocks = <&lvds1_i2c0_lpcg 0>,
+ <&lvds1_i2c0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+ status = "disabled";
+ };
+
+ i2c1_lvds1: i2c@57247000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x57247000 0x1000>;
+ interrupts = <9>;
+ interrupt-parent = <&irqsteer_lvds1>;
+ clocks = <&lvds1_i2c0_lpcg 0>,
+ <&lvds1_i2c0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/seco/include/imx8qm-ss-mipi.dtsi b/arch/arm64/boot/dts/seco/include/imx8qm-ss-mipi.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..ba166abbab3cff419fe366985ca0de8ea46f9818
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qm-ss-mipi.dtsi
@@ -0,0 +1,352 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2019 NXP
+ */
+
+/ {
+ dsi_ipg_clk: clock-dsi-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <120000000>;
+ clock-output-names = "dsi_ipg_clk";
+ };
+
+ mipi_pll_div2_clk: clock-mipi-div2-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <432000000>;
+ clock-output-names = "mipi_pll_div2_clk";
+ };
+
+ mipi0_subsys: bus@56220000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x56220000 0x0 0x56220000 0x10000>;
+
+ mipi0_lis_lpcg: clock-controller@56223000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ bit-offset = <0>;
+ clock-output-names = "mipi0_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ };
+
+ mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5622301c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
+ bit-offset = <0>;
+ clock-output-names = "mipi0_i2c0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ };
+
+ mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223018 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ bit-offset = <0>;
+ clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ };
+
+ mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi0_i2c0_lpcg_ipg_s_clk 0>;
+ bit-offset = <0>;
+ clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ };
+
+ mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5622302c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
+ bit-offset = <0>;
+ clock-output-names = "mipi0_i2c1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
+ };
+
+ mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223028 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ bit-offset = <0>;
+ clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
+ };
+
+ mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223024 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi0_i2c1_lpcg_ipg_s_clk 0>;
+ bit-offset = <0>;
+ clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
+ };
+
+ irqsteer_mipi0: irqsteer@56220000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x56220000 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ clocks = <&mipi0_lis_lpcg 0>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ };
+
+ i2c0_mipi0: i2c@56226000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x56226000 0x1000>;
+ interrupts = <8>;
+ interrupt-parent = <&irqsteer_mipi0>;
+ clocks = <&mipi0_i2c0_lpcg_clk 0>,
+ <&mipi0_i2c0_lpcg_ipg_clk 0>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&mipi0_i2c0_lpcg_clk 0>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ status = "disabled";
+ };
+
+ mipi0_csr: csr@56221000 {
+ compatible = "syscon";
+ reg = <0x56221000 0x240>;
+ };
+
+ mipi0_dphy: dphy@56228300 {
+ compatible = "fsl,imx8qm-mipi-dphy";
+ reg = <0x56228300 0x100>;
+ clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>;
+ clock-names = "phy_ref";
+ #phy-cells = <0>;
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ status = "disabled";
+ };
+
+ mipi0_dsi_host: dsi_host@56228000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qm-nwl-dsi";
+ reg = <0x56228000 0x300>;
+ clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>,
+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>,
+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&mipi_pll_div2_clk>;
+ clock-names = "pixel",
+ "bypass",
+ "phy_ref",
+ "tx_esc",
+ "rx_esc",
+ "phy_parent";
+ interrupts = <16>;
+ interrupt-parent = <&irqsteer_mipi0>;
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ phys = <&mipi0_dphy>;
+ phy-names = "dphy";
+ csr = <&mipi0_csr>;
+ use-disp-ss;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+ mipi0_dsi_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dpu1_disp0_mipi0>;
+ };
+ };
+ };
+ };
+ };
+
+ mipi1_subsys: bus@57220000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x57220000 0x0 0x57220000 0x10000>;
+
+ mipi1_lis_lpcg: clock-controller@57223000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ bit-offset = <0>;
+ clock-output-names = "mipi1_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ };
+
+ mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5722301c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
+ bit-offset = <0>;
+ clock-output-names = "mipi1_i2c0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ };
+
+ mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223018 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ bit-offset = <0>;
+ clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ };
+
+ mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi1_i2c0_lpcg_ipg_s_clk 0>;
+ bit-offset = <0>;
+ clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ };
+
+ mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5722302c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
+ bit-offset = <0>;
+ clock-output-names = "mipi1_i2c1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
+ };
+
+ mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223028 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ bit-offset = <0>;
+ clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
+ };
+
+ mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223024 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi1_i2c1_lpcg_ipg_s_clk 0>;
+ bit-offset = <0>;
+ clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
+ };
+
+ irqsteer_mipi1: irqsteer@57220000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x57220000 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ clocks = <&mipi1_lis_lpcg 0>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ };
+
+ i2c0_mipi1: i2c@57226000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x57226000 0x1000>;
+ interrupts = <8>;
+ interrupt-parent = <&irqsteer_mipi1>;
+ clocks = <&mipi1_i2c0_lpcg_clk 0>,
+ <&mipi1_i2c0_lpcg_ipg_clk 0>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&mipi1_i2c0_lpcg_clk 0>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ status = "disabled";
+ };
+
+ mipi1_csr: csr@57221000 {
+ compatible = "syscon";
+ reg = <0x57221000 0x240>;
+ };
+
+ mipi1_dphy: dphy@57228300 {
+ compatible = "fsl,imx8qm-mipi-dphy";
+ reg = <0x57228300 0x100>;
+ clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>;
+ clock-names = "phy_ref";
+ #phy-cells = <0>;
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ status = "disabled";
+ };
+
+ mipi1_dsi_host: dsi_host@57228000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qm-nwl-dsi";
+ reg = <0x57228000 0x300>;
+ clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>,
+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>,
+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>,
+ <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>,
+ <&mipi_pll_div2_clk>;
+ clock-names = "pixel",
+ "bypass",
+ "phy_ref",
+ "tx_esc",
+ "rx_esc",
+ "phy_parent";
+ interrupts = <16>;
+ interrupt-parent = <&irqsteer_mipi1>;
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ phys = <&mipi1_dphy>;
+ phy-names = "dphy";
+ csr = <&mipi1_csr>;
+ use-disp-ss;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+ mipi1_dsi_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dpu2_disp0_mipi1>;
+ };
+ };
+ };
+ };
+ };
+};
+
diff --git a/arch/arm64/boot/dts/seco/include/imx8qm.dtsi b/arch/arm64/boot/dts/seco/include/imx8qm.dtsi
new file mode 100755
index 0000000000000000000000000000000000000000..cc7b597f99e9c0a87696f453a33a7a521adaa112
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/include/imx8qm.dtsi
@@ -0,0 +1,528 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/clock/imx8-clock.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/pads-imx8qm.h>
+#include <dt-bindings/soc/imx8_hsio.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &fec2;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial2 = &lpuart2;
+ serial3 = &lpuart3;
+ serial4 = &lpuart4;
+ isi0 = &isi_0;
+ isi1 = &isi_1;
+ isi2 = &isi_2;
+ isi3 = &isi_3;
+ isi4 = &isi_4;
+ isi5 = &isi_5;
+ isi6 = &isi_6;
+ isi7 = &isi_7;
+ csi0 = &mipi_csi_0;
+ csi1 = &mipi_csi_1;
+ mu0 = &lsio_mu0;
+ mu1 = &lsio_mu1;
+ mu2 = &lsio_mu2;
+ mu3 = &lsio_mu3;
+ mu4 = &lsio_mu4;
+ can0 = &flexcan1;
+ can1 = &flexcan2;
+ can2 = &flexcan3;
+ dpu0 = &dpu1;
+ dpu1 = &dpu2;
+ ldb0 = &ldb1;
+ ldb1 = &ldb2;
+ i2c0 = &i2c_rpbus_0;
+ i2c1 = &i2c_rpbus_1;
+ dphy0 = &mipi0_dphy;
+ dphy1 = &mipi1_dphy;
+ mipi_dsi0 = &mipi0_dsi_host;
+ mipi_dsi1 = &mipi1_dsi_host;
+ };
+
+ cpus: cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&A53_0>;
+ };
+ core1 {
+ cpu = <&A53_1>;
+ };
+ core2 {
+ cpu = <&A53_2>;
+ };
+ core3 {
+ cpu = <&A53_3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&A72_0>;
+ };
+ core1 {
+ cpu = <&A72_1>;
+ };
+ };
+ };
+
+ A53_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ A53_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ A53_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ A53_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ A72_0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x100>;
+ clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
+ enable-method = "psci";
+ next-level-cache = <&A72_L2>;
+ operating-points-v2 = <&a72_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ A72_1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x101>;
+ clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
+ enable-method = "psci";
+ next-level-cache = <&A72_L2>;
+ operating-points-v2 = <&a72_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ A53_L2: l2-cache0 {
+ compatible = "cache";
+ };
+
+ A72_L2: l2-cache1 {
+ compatible = "cache";
+ };
+ };
+
+ a53_opp_table: a53-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-896000000 {
+ opp-hz = /bits/ 64 <896000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
+ a72_opp_table: a72-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1596000000 {
+ opp-hz = /bits/ 64 <1596000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
+ gic: interrupt-controller@51a00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+ <0x0 0x51b00000 0 0xC0000>, /* GICR */
+ <0x0 0x52000000 0 0x2000>, /* GICC */
+ <0x0 0x52010000 0 0x1000>, /* GICH */
+ <0x0 0x52020000 0 0x20000>; /* GICV */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
+ };
+
+ clk_dummy: clock-dummy {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "clk_dummy";
+ };
+
+ xtal32k: clock-xtal32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xtal_32KHz";
+ };
+
+ xtal24m: clock-xtal24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal_24MHz";
+ };
+
+ smmu: iommu@51400000 {
+ compatible = "arm,mmu-500";
+ interrupt-parent = <&gic>;
+ reg = <0 0x51400000 0 0x40000>;
+ #global-interrupts = <1>;
+ #iommu-cells = <2>;
+ interrupts = <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
+ };
+
+ scu {
+ compatible = "fsl,imx-scu";
+ mbox-names = "tx0",
+ "rx0",
+ "gip3";
+ mboxes = <&lsio_mu1 0 0
+ &lsio_mu1 1 0
+ &lsio_mu1 3 3>;
+
+ pd: imx8qx-pd {
+ compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
+ #power-domain-cells = <1>;
+ wakeup-irq = <235 236 237 258 262 267 271
+ 345 346 347 348>;
+ };
+
+ clk: clock-controller {
+ compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
+ #clock-cells = <2>;
+ clocks = <&xtal32k &xtal24m>;
+ clock-names = "xtal_32KHz", "xtal_24Mhz";
+ };
+
+ iomuxc: pinctrl {
+ compatible = "fsl,imx8qm-iomuxc";
+ };
+
+ ocotp: imx8qm-ocotp {
+ compatible = "fsl,imx8qm-scu-ocotp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ read-only;
+
+ fec_mac0: mac@1c4 {
+ reg = <0x1c4 6>;
+ };
+
+ fec_mac1: mac@1c6 {
+ reg = <0x1c6 6>;
+ };
+ };
+
+ rtc: rtc {
+ compatible = "fsl,imx8qm-sc-rtc";
+ };
+
+ watchdog {
+ compatible = "fsl,imx8qm-sc-wdt", "fsl,imx-sc-wdt";
+ timeout-sec = <60>;
+ };
+
+ tsens: thermal-sensor {
+ compatible = "fsl,imx-sc-thermal";
+ tsens-num = <6>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ secvio: secvio {
+ compatible = "fsl,imx-sc-secvio";
+ nvmem = <&ocotp>;
+ };
+ };
+
+ thermal_zones: thermal-zones {
+ cpu-thermal0 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens IMX_SC_R_A53>;
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <107000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit0: trip1 {
+ temperature = <127000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu-thermal1 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens IMX_SC_R_A72>;
+ trips {
+ cpu_alert1: trip0 {
+ temperature = <107000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit1: trip1 {
+ temperature = <127000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert1>;
+ cooling-device =
+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu-thermal0 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>;
+ trips {
+ gpu_alert0: trip0 {
+ temperature = <107000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ gpu_crit0: trip1 {
+ temperature = <127000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-thermal1 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>;
+ trips {
+ gpu_alert1: trip0 {
+ temperature = <107000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ gpu_crit1: trip1 {
+ temperature = <127000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ drc-thermal0 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens IMX_SC_R_DRC_0>;
+ trips {
+ drc_alert0: trip0 {
+ temperature = <107000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ drc_crit0: trip1 {
+ temperature = <127000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ sc_pwrkey: sc-powerkey {
+ compatible = "fsl,imx8-pwrkey";
+ linux,keycode = <KEY_POWER>;
+ wakeup-source;
+ };
+
+ vpu_subsys_dsp: bus@55000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x55000000 0x0 0x55000000 0x1000000>;
+
+ dsp: dsp@556e8000 {
+ compatible = "fsl,imx8qm-hifi4";
+ reg = <0x556e8000 0x88000>;
+ clocks = <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "dsp_clk1", "dsp_clk2", "dsp_clk3";
+ firmware-name = "imx/dsp/hifi4.bin";
+ power-domains = <&pd IMX_SC_R_MU_13B>,
+ <&pd IMX_SC_R_DSP>,
+ <&pd IMX_SC_R_DSP_RAM>;
+ mbox-names = "tx0", "rx0", "rxdb0";
+ mboxes = <&lsio_mu13 0 0>,
+ <&lsio_mu13 1 0>,
+ <&lsio_mu13 3 0>;
+ status = "disabled";
+ };
+ };
+
+ /* sorted in register address */
+ #include "imx8-ss-security.dtsi"
+ #include "imx8-ss-cm41.dtsi"
+ #include "imx8-ss-adma.dtsi"
+ #include "imx8-ss-conn.dtsi"
+ #include "imx8-ss-ddr.dtsi"
+ #include "imx8-ss-lsio.dtsi"
+ #include "imx8-ss-hsio.dtsi"
+ #include "imx8-ss-img.dtsi"
+ #include "imx8-ss-dc0.dtsi"
+ #include "imx8-ss-dc1.dtsi"
+ #include "imx8-ss-gpu0.dtsi"
+ #include "imx8-ss-gpu1.dtsi"
+ #include "imx8-ss-vpu.dtsi"
+};
+
+#include "imx8qm-ss-audio.dtsi"
+#include "imx8qm-ss-dma.dtsi"
+#include "imx8qm-ss-conn.dtsi"
+#include "imx8qm-ss-ddr.dtsi"
+#include "imx8qm-ss-lsio.dtsi"
+#include "imx8qm-ss-hsio.dtsi"
+#include "imx8qm-ss-dc.dtsi"
+#include "imx8qm-ss-lvds.dtsi"
+#include "imx8qm-ss-mipi.dtsi"
+#include "imx8qm-ss-hdmi.dtsi"
+#include "imx8qm-ss-hdmi-rx.dtsi"
+#include "imx8qm-ss-img.dtsi"
+#include "imx8qm-ss-gpu.dtsi"
diff --git a/arch/arm64/boot/dts/seco/overlays/Makefile b/arch/arm64/boot/dts/seco/overlays/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..89b20900b2da77834537525e4e46a9c404a8800a
--- /dev/null
+++ b/arch/arm64/boot/dts/seco/overlays/Makefile
@@ -0,0 +1,10 @@
+DTC_FLAGS ?= -@ -H epapr
+
+
+
+targets += dtbs dtbs_install
+targets += $(dtbo-y)
+
+always := $(dtbo-y)
+clean-files := *.dtbo
+