diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ec0f6589af05e3ae4b838e5361e22c5a4ef81ae7..d3f2de37a4b7c2305757c768b4cf46ba1dcc2bb7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1213,6 +1213,17 @@ config ARM_ERRATA_754322
 	  the new ASID. This workaround places two dsb instructions in the mm
 	  switching code so that no page table walks can cross the ASID switch.
 
+config ARM_ERRATA_754327
+	bool "ARM errata: no automatic Store Buffer drain"
+	depends on CPU_V7 && SMP
+	help
+	  This option enables the workaround for the 754327 Cortex-A9 (prior to
+	  r2p0) erratum. The Store Buffer does not have any automatic draining
+	  mechanism and therefore a livelock may occur if an external agent
+	  continuously polls a memory location waiting to observe an update.
+	  This workaround defines cpu_relax() as smp_mb(), preventing correctly
+	  written polling loops from denying visibility of updates to memory.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 67357baaeeebd93417932c70ca0d370d17818f51..7a1f03c10f1b1069d39f503f5c485e3a86b066ea 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -95,7 +95,7 @@ extern void release_thread(struct task_struct *);
 
 unsigned long get_wchan(struct task_struct *p);
 
-#if __LINUX_ARM_ARCH__ == 6
+#if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
 #define cpu_relax()			smp_mb()
 #else
 #define cpu_relax()			barrier()